公开(公告)号：US12204774B2

公开(公告)日：2025-01-21

申请号：US17986623

申请日：2022-11-14

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Alexandru Dutu ,  Nuwan Jayasena ,  Yasuko Eckert ,  Niti Madan ,  Sooraj Puthoor

IPC: G06F3/06

Abstract: An apparatus includes a memory controller that includes logic to receive a first memory request having a first request type and a second memory request having a second request type. The apparatus also includes a scheduling unit that includes logic to schedule an order of the first and second memory requests for execution based upon a first parameter value and a second parameter value. The first parameter value corresponds to a utility and energy cost for the first memory request and the second parameter value corresponds to a utility and energy cost for the second memory request.

公开(公告)号：US20250004826A1

公开(公告)日：2025-01-02

申请号：US18214733

申请日：2023-06-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Niti Madan

IPC: G06F9/48 ,  G06F12/08

Abstract: Scheduling requests of multiple processing-in-memory threads and requests of multiple non-processing-in-memory threads is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory threads and a plurality of non-processing-in-memory threads from a host. The memory controller schedules an order of execution for requests of the plurality of processing-in-memory threads and requests of the plurality of non-processing-in-memory threads based on a priority associated with each of the requests and a current operating mode of the system. Requests are maintained in queues at the memory controller and are individually assigned a priority level based on time enqueued at the memory controller. Requests of a different mode than a current operating mode of the system are delayed for scheduling until at least one different mode request is escalated to a maximum priority value, at which point the memory controller initiates a system mode switch.

公开(公告)号：US20240103745A1

公开(公告)日：2024-03-28

申请号：US17954784

申请日：2022-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Niti Madan ,  Johnathan Robert Alsop ,  Alexandru Dutu ,  Mahzabeen Islam ,  Yasuko Eckert ,  Nuwan S Jayasena

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory controller coupled to a memory module receives both processing-in-memory (PIM) requests and memory requests from a host (e.g., a host processor). The memory controller issues PIM requests to one group of memory banks and concurrently issues memory requests to one or more other groups of memory banks. Accordingly, memory requests are performed on groups of memory banks that would otherwise be idle while PIM requests are performed on the one group of memory banks. Optionally, the memory controller coupled to the memory module also takes various actions when switching between operating in a PIM mode and a non-processing-in-memory mode to reduce or hide overhead when switching between the two modes.

公开(公告)号：US11726918B2

公开(公告)日：2023-08-15

申请号：US17361145

申请日：2021-06-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Johnathan Alsop ,  Alexandru Dutu ,  Shaizeen Aga ,  Nuwan Jayasena

IPC: G06F12/0871 ,  G06F12/02 ,  G06F12/084 ,  G06F12/0846

CPC classification number: G06F12/0871 ,  G06F12/0238 ,  G06F12/084 ,  G06F12/0846

Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.

公开(公告)号：US20230205705A1

公开(公告)日：2023-06-29

申请号：US17561406

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Matthew R. Poremba ,  Alexandru Dutu ,  Sooraj Puthoor

IPC: G06F12/10

CPC classification number: G06F12/10

Abstract: An approach provides indirect addressing support for PIM. Indirect PIM commands include address translation information that allows memory modules to perform indirect addressing. Processing logic in a memory module processes an indirect PIM command and retrieves, from a first memory location, a virtual address of a second memory location. The processing logic calculates a corresponding physical address for the virtual address using the address translation information included with the indirect PIM command and retrieves, from the second memory location, a virtual address of a third memory location. This process is repeated any number of times until one or more indirection stop criteria are satisfied. The indirection stop criteria stop the process when work has been completed normally or to prevent errors. Implementations include the processing logic in the memory module working in cooperation with a memory controller to perform indirect addressing.

公开(公告)号：US11288095B2

公开(公告)日：2022-03-29

申请号：US16588872

申请日：2019-09-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Matthew D. Sinclair ,  Bradford M. Beckmann ,  David A. Wood

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/52

Abstract: A technique for synchronizing workgroups is provided. The techniques comprise detecting that one or more non-executing workgroups are ready to execute, placing the one or more non-executing workgroups into one or more ready queues based on the synchronization status of the one or more workgroups, detecting that computing resources are available for execution of one or more ready workgroups, and scheduling for execution one or more ready workgroups from the one or more ready queues in an order that is based on the relative priority of the ready queues.

公开(公告)号：US20240220160A1

公开(公告)日：2024-07-04

申请号：US18148000

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Sooraj Puthoor

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0656 ,  G06F3/0658 ,  G06F3/0679

Abstract: Scheduling processing-in-memory transactions is described. In accordance with the described techniques, a memory controller receives a transaction header from a host, where the transaction header describes a number of operations to be executed by a processing-in-memory component as part of performing the transaction. The memory controller adds the transaction header to a buffer and sends either an acknowledgement message or a negative acknowledgement message to the host, based on a current load of the processing-in-memory component. The acknowledgement message causes the host to send operations of the transaction for execution by the processing-in-memory component and the negative acknowledgement message causes the host to refrain from sending the operations of the transaction for execution by the processing-in-memory component.

公开(公告)号：US20240220107A1

公开(公告)日：2024-07-04

申请号：US18090916

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Nuwan S Jayasena ,  Niti Madan

IPC: G06F3/06

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0673

Abstract: Adaptive scheduling of memory requests and processing-in-memory requests is described. In accordance with the described techniques, a memory controller receives a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from a host. The memory controller schedules an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold. In response to a system switching (e.g., from executing processing-in-memory requests to executing non-processing-in-memory requests or from executing non-processing-in-memory requests to executing processing-in-memory requests), the memory controller modifies the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold. The memory controller continues scheduling an order of execution for subsequent requests received from the host using the modified stall thresholds.

公开(公告)号：US20240045718A1

公开(公告)日：2024-02-08

申请号：US18488794

申请日：2023-10-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Marcus Nathaniel Chow ,  Matthew D. Sinclair ,  Bradford M. Beckmann ,  David A. Wood

IPC: G06F9/48 ,  G06F9/54 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/545 ,  G06F9/3838

Abstract: Techniques for executing workgroups are provided. The techniques include executing, for a first workgroup of a first kernel dispatch, a workgroup dependency instruction that includes an indication to prioritize execution of a second workgroup of a second kernel dispatch, and in response to the workgroup dependency instruction, dispatching the second workgroup of the second kernel dispatch prior to dispatching a third workgroup of the second kernel dispatch, wherein no workgroup dependency instruction including an indication to prioritize execution of the third workgroup has been executed.

公开(公告)号：US20200379820A1

公开(公告)日：2020-12-03

申请号：US16425881

申请日：2019-05-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexandru Dutu ,  Sergey Blagodurov ,  Anthony T. Gutierrez ,  Matthew D. Sinclair ,  David A. Wood ,  Bradford M. Beckmann

IPC: G06F9/52 ,  G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: A technique for synchronizing workgroups is provided. Multiple workgroups execute a wait instruction that specifies a condition variable and a condition. A workgroup scheduler stops execution of a workgroup that executes a wait instruction and an advanced controller begins monitoring the condition variable. In response to the advanced controller detecting that the condition is met, the workgroup scheduler determines whether there is a high contention scenario, which occurs when the wait instruction is part of a mutual exclusion synchronization primitive and is detected by determining that there is a low number of updates to the condition variable prior to detecting that the condition has been met. In a high contention scenario, the workgroup scheduler wakes up one workgroup and schedules another workgroup to be woken up at a time in the future. In a non-contention scenario, more than one workgroup can be woken up at the same time.