公开(公告)号：US10096081B2

公开(公告)日：2018-10-09

申请号：US15270679

申请日：2016-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Fuad Ashkar ,  Harry J. Wise ,  Rex Eldon McCrary ,  Angel E. Socarras

IPC: G06T1/00 ,  G06F15/00 ,  G06T1/20 ,  G06F1/32 ,  G06F3/06 ,  G06T1/60

Abstract: An adaptive list stores previously received hardware state information that has been used to configure a graphics processing core. One or more filters are configured to filter packets from a packet stream directed to the graphics processing core. The packets are filtered based on a comparison of hardware state information included in the packet and hardware state information stored in the adaptive list. The adaptive list is modified in response to filtering the first packet. The filters can include a hardware filter and a software filter that selectively filters the packets based on whether the graphics processing core is limiting throughput. The adaptive list can be implemented as content-addressable memory (CAM), a cache, or a linked list.

公开(公告)号：US20240087078A1

公开(公告)日：2024-03-14

申请号：US18337322

申请日：2023-06-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Fuad Ashkar ,  Vishrut Vaibhav ,  Manu Rastogi ,  Harry J. Wise

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06T15/40

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T15/005 ,  G06T15/40

Abstract: Methods, devices, and systems for rendering primitives in a frame. During a visibility pass, state packets are processed to determine a register state, and the register state is stored in a memory device. During a rendering pass, the state packets are discarded and the register state is read from the memory device. In some implementations, a graphics pipeline is configured during the visibility pass based on the register state determined by processing the state packets, and the graphics pipeline is configured during the rendering pass based on the register state read from the memory device. In some implementations, replay control packets, draw packets, and the state packets, from a packet stream, are processed during the visibility pass; the draw packets are modified based on visibility information determined during the visibility pass; and the replay control packets and draw packets are processed, during the rendering pass.

公开(公告)号：US11169811B2

公开(公告)日：2021-11-09

申请号：US16426613

申请日：2019-05-30

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Rex Eldon McCrary ,  Yi Luo ,  Harry J. Wise ,  Alexander Fuad Ashkar ,  Michael Mantor

IPC: G06F9/38 ,  G06T1/60 ,  G06T1/20 ,  G06F16/245

Abstract: A method of context bouncing includes receiving, at a command processor of a graphics processing unit (GPU), a conditional execute packet providing a hash identifier corresponding to an encapsulated state. The encapsulated state includes one or more context state packets following the conditional execute packet. A command packet following the encapsulated state is executed based at least in part on determining whether the hash identifier of the encapsulated state matches one of a plurality of hash identifiers of active context states currently stored at the GPU.

公开(公告)号：US20210304349A1

公开(公告)日：2021-09-30

申请号：US17028803

申请日：2020-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Anirudh Rajendra Acharya ,  Ruijin Wu ,  Alexander Fuad Ashkar ,  Harry J. Wise

IPC: G06T1/20 ,  G06T7/60 ,  G06F9/38 ,  G06F9/54

Abstract: A technique for executing commands for an accelerated processing device is provided. The technique includes obtaining an iteration number and predication data from metadata for an iterative indirect command buffer; for each iteration indicated by the iteration number, performing commands of the iterative indirect command buffer as specified by the predication data; and ending processing of the iterative indirect command buffer in response to processing a number of iterations equal to the iteration number.

公开(公告)号：US10198849B1

公开(公告)日：2019-02-05

申请号：US15794344

申请日：2017-10-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander Fuad Ashkar ,  Rex Eldon McCrary ,  Harry J. Wise

IPC: G06T1/60 ,  G06T15/00 ,  G06F12/0811 ,  G06F12/1027 ,  G06F12/1009 ,  G06F12/1081 ,  G09G5/39 ,  G09G5/36 ,  G06F13/28

Abstract: Systems, apparatuses, and methods for preloading caches using a direct memory access (DMA) engine with a fast discard mode are disclosed. In one embodiment, a processor includes one or more compute units, a DMA engine, and one or more caches. When a shader program is detected in a sequence of instructions, the DMA engine is programmed to utilize a fast discard mode to prefetch the shader program from memory. By prefetching the shader program from memory, the one or more caches are populated with address translations and the shader program. Then, the DMA engine discards the shader program rather than writing the shader program to another location. Accordingly, when the shader program is invoked on the compute unit(s), the shader program and its translations are already preloaded in the cache(s).

公开(公告)号：US10180789B2

公开(公告)日：2019-01-15

申请号：US15417011

申请日：2017-01-26

Applicant: Advanced Micro Devices, Inc.

Inventor： Rex Eldon McCrary ,  Michael J. Mantor ,  Alexander Fuad Ashkar ,  Harry J. Wise

IPC: G06F12/00 ,  G06F3/06 ,  G06F9/48 ,  G06F9/50

Abstract: Systems, apparatuses, and methods for implementing software control of state sets are disclosed. In one embodiment, a processor includes at least an execution unit and a plurality of state registers. The processor is configured to detect a command to allocate a first state set for storing a first state, wherein the command is generated by software, and wherein the first state specifies values for the plurality of state registers. The command is executed on the execution unit while the processor is in a second state, wherein the second state is different from the first state. The first state set of the processor is allocated with the first state responsive to executing the command on the execution unit. The processor is configured to allocate the first state set for the first state prior to the processor entering the first state.