公开(公告)号：US11726837B2

公开(公告)日：2023-08-15

申请号：US17519290

申请日：2021-11-04

Applicant: Advanced Micro Devices, Inc.

Inventor： Karthik Rao ,  Shomit N. Das ,  Xudong An ,  Wei Huang

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/38 ,  H04L67/12 ,  G06F1/3206 ,  G06F13/40 ,  G06F3/06 ,  H04N19/436

CPC classification number: G06F9/5094 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/4893 ,  G06F9/5011 ,  G06F9/5027 ,  G06F9/5055 ,  H04L67/12 ,  G06F1/3206 ,  G06F3/0613 ,  G06F9/5061 ,  G06F13/409 ,  H04N19/436

Abstract: In some examples, thermal aware optimization logic determines a characteristic (e.g., a workload or type) of a wavefront (e.g., multiple threads). For example, the characteristic indicates whether the wavefront is compute intensive, memory intensive, mixed, and/or another type of wavefront. The thermal aware optimization logic determines temperature information for one or more compute units (CUs) in one or more processing cores. The temperature information includes predictive thermal information indicating expected temperatures corresponding to the one or more CUs and historical thermal information indicating current or past thermal temperatures of at least a portion of a graphics processing unit (GPU). The logic selects the one or more compute units to process the plurality of threads based on the determined characteristic and the temperature information. The logic provides instructions to the selected subset of the plurality of CUs to execute the wavefront.

公开(公告)号：US11436060B2

公开(公告)日：2022-09-06

申请号：US16552065

申请日：2019-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Karthik Rao ,  Abhinav Vishnu

IPC: G06F9/46 ,  G06F9/50 ,  G06N3/08 ,  G06F9/54 ,  G06F9/38

Abstract: Systems, apparatuses, and methods for proactively managing inter-processor network links are disclosed. A computing system includes at least a control unit and a plurality of processing units. Each processing unit of the plurality of processing units includes a compute module and a configurable link interface. The control unit dynamically adjusts a clock frequency and a link width of the configurable link interface of each processing unit based on a data transfer size and layer computation time of a plurality of layers of a neural network so as to reduce execution time of each layer. By adjusting the clock frequency and the link width of the link interface on a per-layer basis, the overlapping of communication and computation phases is closely matched, allowing layers to complete more quickly.

公开(公告)号：US20220100249A1

公开(公告)日：2022-03-31

申请号：US17127681

申请日：2020-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

IPC: G06F1/28 ,  G06F1/30 ,  G01R31/40

Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

公开(公告)号：US10560022B2

公开(公告)日：2020-02-11

申请号：US16440838

申请日：2019-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Miguel Rodriguez ,  Karthik Rao

IPC: H02M3/158 ,  G05F1/575 ,  G05F1/46 ,  G05F1/56 ,  H02M1/00

Abstract: An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.

公开(公告)号：US11556250B2

公开(公告)日：2023-01-17

申请号：US16939814

申请日：2020-07-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Jagadish B. Kotra ,  Karthik Rao ,  Joseph L. Greathouse

IPC: G06F3/06

Abstract: A system including a stack of two or more layers of volatile memory, such as layers of a 3D stacked DRAM memory, places data in the stack based on a temperature or a refresh rate. When a threshold is exceeded, data are moved from a first region to a second region in the stack, the second region having one or both of a second temperature lower than a first temperature of the first region or a second refresh rate lower than a first refresh rate of the first region.

公开(公告)号：US11886224B2

公开(公告)日：2024-01-30

申请号：US16945519

申请日：2020-07-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Leonardo De Paula Rosa Piga ,  Karthik Rao ,  Indrani Paul ,  Mahesh Subramony ,  Kenneth Mitchell ,  Dana Glenn Lewis ,  Sriram Sambamurthy ,  Wonje Choi

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/30

CPC classification number: G06F9/5027 ,  G06F9/48 ,  G06F9/4806 ,  G06F9/4843 ,  G06F9/4881 ,  G06F9/4893 ,  G06F9/50 ,  G06F9/5005 ,  G06F9/5011 ,  G06F9/5033 ,  G06F9/5044 ,  G06F9/5055 ,  G06F9/5094 ,  G06F9/30098 ,  G06F2209/5021

Abstract: A processing unit of a processing system compiles a priority queue listing of a plurality of processor cores to run a workload based on a cost of running the workload on each of the processor cores. The cost is based on at least one of a system usage policy, characteristics of the workload, and one or more physical constraints of each processor core. The processing unit selects a processor core based on the cost to run the workload and communicates an identifier of the selected processor core to an operating system of the processing system.

公开(公告)号：US11829222B2

公开(公告)日：2023-11-28

申请号：US17127681

申请日：2020-12-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

IPC: G06F1/28 ,  G01R31/40 ,  G06F1/30

CPC classification number: G06F1/28 ,  G01R31/40 ,  G06F1/30

Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

公开(公告)号：US20190296644A1

公开(公告)日：2019-09-26

申请号：US16440838

申请日：2019-06-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Wei Huang ,  Miguel Rodriguez ,  Karthik Rao

IPC: H02M3/158 ,  G05F1/56 ,  G05F1/46 ,  G05F1/575

Abstract: An apparatus includes an integrated circuit chip with a set of circuits having two or more subsets of circuits; an external voltage regulator separate from the integrated circuit chip; two or more integrated voltage regulators on the integrated circuit chip that each provide an input voltage to a respective subset of the circuits; and a controller. The controller determines, using an integrated voltage regulator power loss model, an electrical power loss for the integrated voltage regulators for a first combination of operating points for the subsets of the circuits. The controller then determines, based on the electrical power loss, a second combination of operating points for the subsets of the circuits that includes an adjustment to an operating point for at least one of the subsets of the circuits that compensates for an electrical power loss of the corresponding integrated voltage regulator. The controller sets an operating point of each of the subsets of the circuits based on the second combination of operating points.