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    OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS
    3.
    发明申请
    OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS 有权

    公开(公告)号：US20220100249A1

    公开(公告)日：2022-03-31

    申请号：US17127681

    申请日：2020-12-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

    IPC: G06F1/28 ,  G06F1/30 ,  G01R31/40

    Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

    Low insertion delay clock doubler and integrated circuit clock distribution system using same
    4.
    发明授权
    Low insertion delay clock doubler and integrated circuit clock distribution system using same 有权
    低插入延迟时钟倍频器和集成电路时钟分配系统使用相同

    公开(公告)号：US09372499B2

    公开(公告)日：2016-06-21

    申请号：US14159967

    申请日：2014-01-21

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sriram Sambamurthy ,  Arun Sundaresan Iyer ,  Alok Baluni ,  Aaron Grenat

    IPC: H03B19/00 ,  G06F1/04 ,  H03K19/20 ,  H03K5/00 ,  H03K19/00

    CPC classification number: G06F1/04 ,  G06F1/10 ,  H03K5/00006 ,  H03K19/0013 ,  H03K19/20

    Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.

    Abstract translation: 时钟倍频器包括具有用于接收时钟输入信号和第二输入的第一输入的第一NAND门，具有第一输入和第二输入的第二NAND门，用于接收时钟输入信号的补码;输出NAND门，具有 分别耦合到第一和非门的输出的第一和第二输入以及用于提供时钟输出信号的输出，具有用于接收时钟输入信号的输入的反相器链，并响应第一和第二控制信号选择性地 向第二NAND门的第一输入提供第一真实输出，以及向第一NAND门的第二输入提供第二互补输出;以及控制信号生成电路，响应于第一NAND门的输出而提供第一和第二控制信号 第一和第二NAND门。

    LOW POWER PROCESSING OF REMOTE MANAGEABILITY REQUESTS
    9.
    发明公开
    LOW POWER PROCESSING OF REMOTE MANAGEABILITY REQUESTS 审中-公开

    公开(公告)号：US20240113914A1

    公开(公告)日：2024-04-04

    申请号：US17937262

    申请日：2022-09-30

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sriram Sambamurthy ,  Indrani Paul ,  David Boardman Kramer ,  Madhusudan Chilakam

    IPC: H04L12/46 ,  H04L49/109

    CPC classification number: H04L12/4616 ,  H04L49/109

    Abstract: An apparatus and method for efficiently performing power management for multiple clients of a semiconductor chip that supports remote manageability. In various implementations, a network interface receives a packet, and sends at least an indication of the packet to a manageability processing circuitry (MPC) of a processing node with multiple clients for processing tasks. The MPC determines whether a client or itself is a destination needed to process the packet. If the destination is the MPC, then packet processing is done by the MPC without involvement from the clients, which can be in an idle state. For example, the MPC can process a remote manageability packet requesting diagnostic information from one or more clients of the processing node. The network interface and the MPC use a sideband communication channel for data transmission, which foregoes lane training for further reduction in latency and power consumption.

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