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    Page migration acceleration using a two-level bloom filter on high bandwidth memory systems
    2.
    发明授权
    Page migration acceleration using a two-level bloom filter on high bandwidth memory systems 有权

    公开(公告)号：US10067709B2

    公开(公告)日：2018-09-04

    申请号：US15269289

    申请日：2016-09-19

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Leonardo Piga ,  Mauricio Breternitz

    IPC: G06F12/00 ,  G06F3/06 ,  G06F17/30 ,  G06F13/00 ,  G06F13/28

    Abstract: Systems, apparatuses, and methods for accelerating page migration using a two-level bloom filter are disclosed. In one embodiment, a system includes a GPU and a CPU and a multi-level memory hierarchy. When a memory request misses in a first memory, the GPU is configured to check a first level of a two-level bloom filter to determine if a page targeted by the memory request is located in a second memory. If the first level of the two-level bloom filter indicates that the page is not in the second memory, then the GPU generates a page fault and sends the memory request to a third memory. If the first level of the two-level bloom filter indicates that the page is in the second memory, then the GPU sends the memory request to the CPU.

    Managing cluster-level performance variability without a centralized controller
    4.
    发明授权
    Managing cluster-level performance variability without a centralized controller 有权

    公开(公告)号：US10237335B2

    公开(公告)日：2019-03-19

    申请号：US15183625

    申请日：2016-06-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Leonardo Piga

    IPC: G06F9/00 ,  H04L29/08

    Abstract: Systems, apparatuses, and methods for managing cluster-level performance variability without a centralized controller are described. Each node of a multi-node cluster tracks a maximum and minimum progress across the plurality of nodes for a workload executed by the cluster. Each node also tracks its local progress on its current task. Each node also utilizes a comparison of the local progress to reported maximum and minimum progress across the cluster to identify a critical, or slow, node and whether to increase or reduce an amount of power allocated to the node. The nodes append information about the maximum and minimum progress to messages sent to other nodes to report their knowledge of maximum and minimum progress with other nodes. A node updates its local information if the node receives a message from another node with more up-to-date information about the state of progress across the cluster.

    BANDWIDTH-AWARE MULTI-FREQUENCY PERFORMANCE ESTIMATION MECHANISM
    5.
    发明申请
    BANDWIDTH-AWARE MULTI-FREQUENCY PERFORMANCE ESTIMATION MECHANISM 审中-公开

    公开(公告)号：US20180210531A1

    公开(公告)日：2018-07-26

    申请号：US15416993

    申请日：2017-01-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Md Abdullah Shahneous Bari ,  Leonardo Piga ,  Indrani Paul

    IPC: G06F1/32 ,  G06F3/06

    CPC classification number: G06F1/324 ,  G06F3/0604 ,  G06F3/0611 ,  G06F3/0625 ,  G06F3/0629 ,  G06F3/0673

    Abstract: Systems, apparatuses, and methods for implementing performance estimation mechanisms are disclosed. In one embodiment, a computing system includes at least one processor and a memory subsystem. During a characterization phase, the system utilizes a memory intensive workload to detect when the memory subsystem reaches its saturation point. Then, the system collects performance counter values during a sampling phase of a target application to determine the memory bandwidth. If the memory bandwidth is greater than the saturation point, then the system generates a prediction of the memory time which is based on a ratio of the memory bandwidth over the saturation point. Otherwise, if the memory bandwidth is less than the saturation point, the system assumes memory time is constant versus processor frequency. Then, the system uses the memory time and an estimate of the compute time to estimate a phase time for the target application at different processor frequencies.

    TEMPERATURE-AWARE TASK SCHEDULING AND PROACTIVE POWER MANAGEMENT
    6.
    发明申请
    TEMPERATURE-AWARE TASK SCHEDULING AND PROACTIVE POWER MANAGEMENT 审中-公开

    公开(公告)号：US20170371719A1

    公开(公告)日：2017-12-28

    申请号：US15192784

    申请日：2016-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Abhinandan Majumdar ,  Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Yasuko Eckert

    IPC: G06F9/50 ,  G06F1/32

    CPC classification number: G06F9/4893 ,  G06F1/206 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/24

    Abstract: Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The SoC also determines a thermal gradient for each processing unit to predict a rate at which the processing unit's temperature will change when executing a task. The SoC also monitors a thermal margin of how far each processing unit is from reaching its thermal limit. The SoC minimizes non-uniform heat generation on the SoC by scheduling pending tasks from the task queue to the processing units based on the thermal metrics for the pending tasks, the thermal gradients of each processing unit, and the thermal margin available on each processing unit.

    BALANCING COMPUTATION AND COMMUNICATION POWER IN POWER CONSTRAINED CLUSTERS
    7.
    发明申请
    BALANCING COMPUTATION AND COMMUNICATION POWER IN POWER CONSTRAINED CLUSTERS 有权

    公开(公告)号：US20170160781A1

    公开(公告)日：2017-06-08

    申请号：US14959669

    申请日：2015-12-04

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Leonardo Piga ,  Indrani Paul ,  Wei Huang

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/3287 ,  Y02D10/171

    Abstract: Systems, apparatuses, and methods for balancing computation and communication power in power constrained environments. A data processing cluster with a plurality of compute nodes may perform parallel processing of a workload in a power constrained environment. Nodes that finish tasks early may be power-gated based on one or more conditions. In some scenarios, a node may predict a wait duration and go into a reduced power consumption state if the wait duration is predicted to be greater than a threshold. The power saved by power-gating one or more nodes may be reassigned for use by other nodes. A cluster agent may be configured to reassign the unused power to the active nodes to expedite workload processing.

    OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS
    9.
    发明申请
    OPERATING VOLTAGE ADJUSTMENT FOR AGING CIRCUITS 有权

    公开(公告)号：US20220100249A1

    公开(公告)日：2022-03-31

    申请号：US17127681

    申请日：2020-12-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Sriram Sambamurthy ,  Sriram Sundaram ,  Indrani Paul ,  Larry David Hewitt ,  Anil Harwani ,  Aaron Joseph Grenat ,  Dana Glenn Lewis ,  Leonardo Piga ,  Wonje Choi ,  Karthik Rao

    IPC: G06F1/28 ,  G06F1/30 ,  G01R31/40

    Abstract: A system and method for updating power supply voltages due to variations from aging are described. A functional unit includes a power supply monitor capable of measuring power supply variations in a region of the functional unit. An age counter measures an age of the functional unit. A control unit notifies the power supply monitor to measure an operating voltage reference. When the control unit receives a measured operating voltage reference, the control unit determines an updated age of the region different from the current age based on the measured operating voltage reference. The control unit updates the age counter with the corresponding age, which is younger than the previous age in some cases due to the region not experiencing predicted stress and aging. The control unit is capable of determining a voltage adjustment for the operating voltage reference based on an age indicated by the age counter.

    Temperature-aware task scheduling and proactive power management
    10.
    发明授权
    Temperature-aware task scheduling and proactive power management 有权

    公开(公告)号：US10452437B2

    公开(公告)日：2019-10-22

    申请号：US15192784

    申请日：2016-06-24

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Abhinandan Majumdar ,  Brian J. Kocoloski ,  Leonardo Piga ,  Wei Huang ,  Yasuko Eckert

    IPC: G06F9/48 ,  G06F9/50 ,  G06F1/20 ,  G06F1/329

    Abstract: Systems, apparatuses, and methods for performing temperature-aware task scheduling and proactive power management. A SoC includes a plurality of processing units and a task queue storing pending tasks. The SoC calculates a thermal metric for each pending task to predict an amount of heat the pending task will generate. The SoC also determines a thermal gradient for each processing unit to predict a rate at which the processing unit's temperature will change when executing a task. The SoC also monitors a thermal margin of how far each processing unit is from reaching its thermal limit. The SoC minimizes non-uniform heat generation on the SoC by scheduling pending tasks from the task queue to the processing units based on the thermal metrics for the pending tasks, the thermal gradients of each processing unit, and the thermal margin available on each processing unit.

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