公开(公告)号：US20220101914A1

公开(公告)日：2022-03-31

申请号：US17317844

申请日：2021-05-11

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Ajay Bhatia ,  Michael R. Seningen ,  Greg M. Hess ,  Siddhesh Gaiki

IPC: G11C11/412 ,  G11C11/419 ,  G06F7/523

Abstract: A compute-memory circuit included in a computer system may include multiple compute data storage cells coupled to a compute bit line via respective capacitors. The compute data storage cells may store respective bits of a weight value. During a multiply operation, an operand may be used to generate a voltage level on a compute word line that is used to store respective amounts of charge on the capacitors, which are coupled to the compute bit line. The voltage on the compute bit line may be converted into multiple bits whose value is indicative of a product of the operand and the weight value.

公开(公告)号：US10340900B2

公开(公告)日：2019-07-02

申请号：US15389332

申请日：2016-12-22

Applicant: Apple Inc.

Inventor： Amrinder S. Barn ,  Bo Zhao ,  Michael A. Dreesen

IPC: G11C7/00 ,  H03F3/45 ,  H03K3/00 ,  H03K3/356 ,  H03K19/0175 ,  G11C29/32 ,  G11C7/10

Abstract: In an embodiment, an apparatus includes a first latch including a true storage node and a complement storage node, a discharge circuit, and a second latch. The first latch may pre-charge the true storage node and the complement storage node to a first voltage level using a clock signal. The discharge circuit may, in response to a determination that a scan mode signal is asserted, selectively discharge either the true storage node or the complement storage node based on a value of a scan data signal, and otherwise may selectively discharge either the true storage node or the complement storage node based on a value of a data signal. The second latch may store a value of a data bit based on a voltage level of the true storage node and a voltage level of the complement storage node.

公开(公告)号：US09529533B1

公开(公告)日：2016-12-27

申请号：US15177596

申请日：2016-06-09

Applicant: Apple Inc.

Inventor： Michael A. Dreesen ,  Naveen Javarappa ,  Ajay Kumar Bhatia ,  Greg M. Hess

IPC: G11C5/14 ,  G06F3/06 ,  G06F1/32 ,  G06F1/26 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/418 ,  G06F1/3275 ,  G06F1/3296 ,  G11C5/14 ,  G11C11/417 ,  G11C11/419 ,  Y02D10/14 ,  Y02D10/172

Abstract: An apparatus for modifying a voltage level of a memory array power supply is disclosed. A first column may include a first plurality of data storage cells coupled to a first local power supply signal and a second column may include a second plurality of data storage cells coupled to a second local power supply signal. A first switch may be configured to selectively coupled the first local power supply signal to either a first power signal or a second power supply signal dependent upon a value of a first selection signal, and a second switch may be configured to selectively couple the second local power supply signal to either the first power supply signal or the second power supply signal dependent upon a value of a second selection signal.

Abstract translation: 公开了一种用于修改存储器阵列电源的电压电平的装置。 第一列可以包括耦合到第一本地电源信号的第一多个数据存储单元，并且第二列可以包括耦合到第二本地电源信号的第二多个数据存储单元。 第一开关可以被配置为根据第一选择信号的值将第一本地电源信号选择性地耦合到第一电源信号或第二电源信号，并且第二开关可被配置为选择性地将第二本地电源信号 根据第二选择信号的值将电源信号提供给第一电源信号或第二电源信号。