公开(公告)号：US20150067246A1

公开(公告)日：2015-03-05

申请号：US14013471

申请日：2013-08-29

Applicant: Apple Inc

Inventor： Muditha Kanchana ,  Odutola O. Ewedemi

IPC: G06F12/08 ,  G11C11/406

CPC classification number: G06F12/0831 ,  G06F12/0822

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a plurality of state memories, a plurality tag memories, and a control circuit. Each of the state memories may be configured to store coherency state information for a cache memory of a respective plurality of coherent agents. Each of the tag memories may be configured to store duplicate tag information a cache memory of the respective plurality of coherent agents. The control circuit may be configured to receive a tag address, access tag information in each of the tag memories in parallel dependent upon the received tag address, determine, for each cache memory, new coherency state information for a cache entry corresponding to the received tag address, and store the new coherency state information for each of the cache memories into a respective one of the plurality of state memories.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括多个状态存储器，多个标签存储器和控制电路。 每个状态存储器可以被配置为存储用于相应多个相干代理的高速缓冲存储器的一致性状态信息。 每个标签存储器可以被配置为将重复的标签信息存储在相应的多个相干代理的高速缓冲存储器中。 控制电路可以被配置为接收标签地址，取决于接收到的标签地址并行地访问每个标签存储器中的标签信息，为每个高速缓冲存储器确定与接收到的标签相对应的高速缓存条目的新的一致性状态信息 地址，并将每个高速缓冲存储器的新的一致性状态信息存储到多个状态存储器的相应一个状态存储器中。

公开(公告)号：US20150006803A1

公开(公告)日：2015-01-01

申请号：US13928636

申请日：2013-06-27

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Odutola O. Ewedemi

IPC: G06F12/08

CPC classification number: G06F12/0815

Abstract: An apparatus for processing cache requests in a computing system is disclosed. The apparatus may include a single-port memory, a dual-port memory, and a control circuit. The single-port memory may be store tag information associated with a cache memory, and the dual-port memory may be configured to store state information associated with the cache memory. The control circuit may be configured to receive a request which includes a tag address, access the tag and state information stored in the single-port memory and the dual-port memory, respectively, dependent upon the received tag address. A determination of if the data associated with the received tag address is contained in the cache memory may be made the control circuit, and the control circuit may update and store state information in the dual-port memory responsive to the determination.

Abstract translation: 公开了一种用于处理计算系统中的缓存请求的装置。 该装置可以包括单端口存储器，双端口存储器和控制电路。 单端口存储器可以是与高速缓冲存储器相关联的存储标签信息，并且双端口存储器可以被配置为存储与高速缓冲存储器相关联的状态信息。 控制电路可以被配置为根据接收的标签地址分别接收包括标签地址，访问标签和分别存储在单端口存储器中的状态信息和双端口存储器的请求。 可以确定与接收的标签地址相关联的数据是否包含在高速缓存存储器中，并且控制电路可以响应于该确定来更新和存储双端口存储器中的状态信息。

公开(公告)号：US20140189411A1

公开(公告)日：2014-07-03

申请号：US13733775

申请日：2013-01-03

Applicant: APPLE INC.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。

公开(公告)号：US11138111B2

公开(公告)日：2021-10-05

申请号：US16129527

申请日：2018-09-12

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Srinivasa Rangan Sridharan ,  Harshavardhan Kaushikkar ,  Sridhar Kotha ,  Brian P. Lilly

IPC: G06F12/0815 ,  G06F12/0884 ,  G06F12/0855

Abstract: Systems, apparatuses, and methods for performing coherence processing and memory cache processing in parallel are disclosed. A system includes a communication fabric and a plurality of dual-processing pipelines. Each dual-processing pipeline includes a coherence processing pipeline and a memory cache processing pipeline. The communication fabric forwards a transaction to a given dual-processing pipeline, with the communication fabric selecting the given dual-processing pipeline, from the plurality of dual-processing pipelines, based on a hash of the address of the transaction. The given dual-processing pipeline performs a duplicate tag lookup in parallel with a memory cache tag lookup for the transaction. By performing the duplicate tag lookup and the memory cache tag lookup in a parallel fashion rather than in a serial fashion, latency and power consumption are reduced while performance is enhanced.

公开(公告)号：US09823730B2

公开(公告)日：2017-11-21

申请号：US14793778

申请日：2015-07-08

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Erik P. Machnicki

IPC: G06F1/32 ,  G06F12/0813 ,  G06F12/0831 ,  G06F12/0817

CPC classification number: G06F1/3275 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.

公开(公告)号：US20170010655A1

公开(公告)日：2017-01-12

申请号：US14793778

申请日：2015-07-08

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Erik P. Machnicki

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F12/0813 ,  G06F12/0822 ,  G06F12/0831 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/314 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A method and apparatus for power management of cache duplicate tags is disclosed. An IC includes a cache, a coherence circuit, and a duplicate tags memory that may store duplicates of the tags stored in the cache. The cache includes a number of ways that are separately and independently power controllable. The duplicate tags memory may be similarly organized, with portions that are power controllable separately and independently of others. The coherence circuit is also power controllable, and may be placed into a sleep mode when idle. The IC also includes a power management circuit. During operation, the cache may change power states and provide a corresponding indication to the power management circuit. Responsive to the indication, the power management circuit may awaken the coherence circuit if in a sleep state. The coherence circuit may then power manage the duplicate tags in accordance with the change in power state.

Abstract translation: 公开了一种缓存重复标签的电源管理方法和装置。 IC包括缓存，相干电路和可以存储存储在高速缓存中的标签的重复的重复标签存储器。 高速缓存包括单独和独立的功率可控的多种方式。 重复的标签存储器可以类似地组织，其中部分功率可以单独地并且独立于其它功能。 相干电路也是功率可控的，并且可以在空闲时被置于睡眠模式。 IC还包括电源管理电路。 在操作期间，高速缓存可以改变功率状态并且向电源管理电路提供相应的指示。 响应于指示，如果处于睡眠状态，则电源管理电路可唤醒相干电路。 然后，相干电路可以根据电源状态的变化来对重复标签进行电源管理。

公开(公告)号：US09317102B2

公开(公告)日：2016-04-19

申请号：US13733775

申请日：2013-01-03

Applicant: Apple Inc.

Inventor： Muditha Kanchana ,  Gurjeet S. Saund ,  Harshavardhan Kaushikkar ,  Erik P. Machnicki ,  Seye Ewedemi

IPC: G06F1/32 ,  G11C5/14

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G11C5/144 ,  Y02D10/14

Abstract: Techniques are disclosed relating to reducing power consumption in integrated circuits. In one embodiment, an apparatus includes a cache having a set of tag structures and a power management unit. The power management unit is configured to power down a duplicate set of tag structures in responsive to the cache being powered down. In one embodiment, the cache is configured to provide, to the power management unit, an indication of whether the cache includes valid data. In such an embodiment, the power management unit is configured to power down the cache in response to the cache indicating that the cache does not include valid data. In some embodiments, the duplicate set of tag structures is located within a coherence point configured to maintain coherency between the cache and a memory.

Abstract translation: 公开了关于降低集成电路中的功耗的技术。 在一个实施例中，一种装置包括具有一组标签结构的缓存和电源管理单元。 功率管理单元被配置为响应于被断电的高速缓存而将重复的一组标签结构断电。 在一个实施例中，高速缓存被配置为向电力管理单元提供高速缓存是否包括有效数据的指示。 在这样的实施例中，功率管理单元被配置为响应于缓存指示高速缓存不包括有效数据的高速缓存来关闭高速缓存。 在一些实施例中，重复的标签结构集合位于被配置为保持高速缓存和存储器之间的一致性的相干点内。

公开(公告)号：US09021306B2

公开(公告)日：2015-04-28

申请号：US13713654

申请日：2012-12-13

Applicant: Apple Inc.

Inventor： Harshavardhan Kaushikkar ,  Muditha Kanchana ,  Gurjeet S Saund ,  Odutola O Ewedemi

IPC: G06F11/00 ,  G06F11/273 ,  G06F11/22

CPC classification number: G06F11/273 ,  G06F11/221 ,  G06F11/2236

Abstract: A coherence system includes a storage array that may store duplicate tag information associated with a cache memory of a processor. The system may also include a pipeline unit that includes a number of stages to control accesses to the storage array. The pipeline unit may pass through the pipeline stages, without generating an access to the storage array, an input/output (I/O) request that is received on a fabric. The system may also include a debug engine that may reformat the I/O request from the pipeline unit into a debug request. The debug engine may send the debug request to the pipeline unit via a debug bus. In response to receiving the debug request, the pipeline unit may access the storage array. The debug engine may return to the source of the I/O request via the fabric bus, a result of the access to the storage array.

Abstract translation: 相干系统包括可存储与处理器的高速缓冲存储器相关联的重复标签信息的存储阵列。 系统还可以包括流水线单元，其包括多个级以控制对存储阵列的访问。 流水线单元可以通过流水线阶段，而不产生对存储阵列的访问，即在结构上接收的输入/输出（I / O）请求。 该系统还可以包括可以将流水线单元的I / O请求重新格式化为调试请求的调试引擎。 调试引擎可以通过调试总线将调试请求发送到流水线单元。 响应于接收到调试请求，流水线单元可以访问存储阵列。 调试引擎可以通过结构总线返回到I / O请求的源，这是访问存储阵列的结果。