公开(公告)号：US09400544B2

公开(公告)日：2016-07-26

申请号：US13855189

申请日：2013-04-02

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Rong Zhang Hu ,  Sukalpa Biswas ,  Shinye Shiu

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section.

Abstract translation: 用于减少存储器控制器内的系统高速缓存中的泄漏功率的方法和装置。 系统高速缓存分为多个部分，每个部分由两个电源电压之一供电。 当一个部分没有被访问时，提供给该部分的电压降低到足以保留数据但不能访问的电压。 高速缓存利用最大允许的有效部分策略来限制在任何给定时间处于活动状态的部分数量以减少泄漏功率。 每个部分包括相应的空闲定时器和休眠平衡定时器。 空闲定时器跟踪该段已经空闲多久，并且使用休眠定时器来定期将段从唤醒模式唤醒，以检查是否有一个针对该段的挂起请求。

公开(公告)号：US20140298058A1

公开(公告)日：2014-10-02

申请号：US13855189

申请日：2013-04-02

Applicant: APPLE INC.

Inventor： Wolfgang H. Klingauf ,  Rong Zhang Hu ,  Sukalpa Biswas ,  Shinye Shiu

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section.

Abstract translation: 用于减少存储器控制器内的系统高速缓存中的泄漏功率的方法和装置。 系统高速缓存分为多个部分，每个部分由两个电源电压之一供电。 当一个部分没有被访问时，提供给该部分的电压降低到足以保留数据但不能访问的电压。 高速缓存利用最大允许的有效部分策略来限制在任何给定时间处于活动状态的部分数量以减少泄漏功率。 每个部分包括相应的空闲定时器和休眠平衡定时器。 空闲定时器跟踪该段已经空闲多久，并且使用休眠定时器来定期将段从唤醒模式唤醒，以检查是否有一个针对该段的挂起请求。

公开(公告)号：US20140297959A1

公开(公告)日：2014-10-02

申请号：US13855174

申请日：2013-04-02

Applicant: APPLE INC.

Inventor： Shinye Shiu ,  Sukalpa Biswas ,  Wolfgang H. Klingauf ,  Rong Zhang Hu

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other ways. A target active way count is maintained and the system cache attempts to keep the number of currently active ways equal to the target active way count. The bandwidth and allocation intention of the system cache is monitored. Based on these characteristics, the system cache adjusts the target active way count up or down, which then causes the number of currently active ways to rise or fall in response to the adjustment to the target active way count.

Abstract translation: 用于降低存储器控制器内的系统高速缓存的功耗的方法和装置。 系统缓存包含多种方式，每种方式独立于其他方式供电。 维护目标活动方式计数，并且系统缓存尝试将当前活动方式的数量保持等于目标活动方式计数。 监控系统缓存的带宽和分配意图。 基于这些特征，系统高速缓存调整目标活动方式向上或向下计数，从而响应于对目标活动方式计数的调整，使当前活动方式的数量上升或下降。

公开(公告)号：US20140089590A1

公开(公告)日：2014-03-27

申请号：US13629563

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Rong Zhang Hu

IPC: G06F12/08

CPC classification number: G06F1/3225 ,  G06F2212/601

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.

Abstract translation: 用于降低存储器控制器内的系统高速缓存的功耗的方法和装置。 系统缓存包含多种方式，缓存活动较低时，各种方式都会关闭。 最大有效方式配置寄存器由软件设置，并确定允许有效的最大路数。 当搜索高速缓存行替换候选时，线性反馈移位寄存器（LFSR）用于从活动方式中选择。 这确保了当一个或多个方式处于非活动状态时，每个活动方式都有相同的机会被选中以找到替换候选。