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公开(公告)号：US09261939B2
公开(公告)日：2016-02-16
申请号：US13890306
申请日：2013-05-09
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
CPC classification number: G06F1/3275 , G06F1/3218 , G06F1/3287 , G06F3/14 , G06F12/0873 , G06F2212/455 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2360/121
Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。
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公开(公告)号：US20140337649A1
公开(公告)日：2014-11-13
申请号：US13890306
申请日：2013-05-09
Applicant: APPLE INC.
Inventor： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3218 , G06F1/3287 , G06F3/14 , G06F12/0873 , G06F2212/455 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2360/121
Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。
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公开(公告)号：US09396122B2
公开(公告)日：2016-07-19
申请号：US13866282
申请日：2013-04-19
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Wolfgang H. Klingauf , Rong Zhang Hu , Shinye Shiu
CPC classification number: G06F12/0871 , G06F1/3218 , G06F1/3275 , G06F12/0864 , G06F12/0893 , G06F12/122 , G06F2212/1028 , G06F2212/171 , G06F2212/6046 , G09G5/395 , G09G2330/021 , G09G2330/022 , G09G2360/121 , Y02D10/13 , Y02D10/14
Abstract: Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.
Abstract translation: 针对浏览应用程序优化的缓存分配方案的方法和系统。 存储器控制器包括用于减少访问片外存储器的请求数量的存储器高速缓存。 当检测到空闲屏幕使用情况时，使用顺序分配模式将帧缓冲器分配给存储器高速缓存。 以依次方式将像素分配给给定方式的索引，然后以顺序的方式访问各种方式。 当访问给定的方式时，存储器高速缓存的其他方式进入保留模式以减少泄漏功率。
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公开(公告)号：US20140317355A1
公开(公告)日：2014-10-23
申请号：US13866282
申请日：2013-04-19
Applicant: APPLE INC.
Inventor： Sukalpa Biswas , Wolfgang H. Klingauf , Rong Zhang Hu , Shinye Shiu
CPC classification number: G06F12/0871 , G06F1/3218 , G06F1/3275 , G06F12/0864 , G06F12/0893 , G06F12/122 , G06F2212/1028 , G06F2212/171 , G06F2212/6046 , G09G5/395 , G09G2330/021 , G09G2330/022 , G09G2360/121 , Y02D10/13 , Y02D10/14
Abstract: Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.
Abstract translation: 针对浏览应用程序优化的缓存分配方案的方法和系统。 存储器控制器包括用于减少访问片外存储器的请求数量的存储器高速缓存。 当检测到空闲屏幕使用情况时，使用顺序分配模式将帧缓冲器分配给存储器高速缓存。 以依次方式将像素分配给给定方式的索引，然后以顺序的方式访问各种方式。 当访问给定的方式时，存储器高速缓存的其他方式进入保留模式以减少泄漏功率。
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公开(公告)号：US10310586B2
公开(公告)日：2019-06-04
申请号：US14980912
申请日：2015-12-28
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
IPC: G06F1/3218 , G06F1/3234 , G06F3/14 , G09G5/00 , G09G5/393 , G09G5/395 , G06F1/3287 , G06F12/0873
Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
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Patent Agency Ranking
公开(公告)号：US20160116969A1
公开(公告)日：2016-04-28
申请号：US14980912
申请日：2015-12-28
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Shinye Shiu , Cyril de la Cropte de Chanterac , Manu Gulati , Pulkit Desai , Rong Zhang Hu
CPC classification number: G06F1/3275 , G06F1/3218 , G06F1/3287 , G06F3/14 , G06F12/0873 , G06F2212/455 , G09G5/001 , G09G5/393 , G09G5/395 , G09G2330/02 , G09G2330/021 , G09G2360/121
Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.
Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。
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公开(公告)号：US09218040B2
公开(公告)日：2015-12-22
申请号：US13629563
申请日：2012-09-27
Applicant: Apple Inc.
Inventor： Sukalpa Biswas , Shinye Shiu , Rong Zhang Hu
IPC: G06F1/32
CPC classification number: G06F1/3225 , G06F2212/601
Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.
Abstract translation: 用于降低存储器控制器内的系统高速缓存的功耗的方法和装置。 系统缓存包含多种方式，缓存活动较低时，各种方式都会关闭。 最大有效方式配置寄存器由软件设置，并确定允许有效的最大路数。 当搜索高速缓存行替换候选时，线性反馈移位寄存器（LFSR）用于从活动方式中选择。 这确保了当一个或多个方式处于非活动状态时，每个活动方式都有相同的机会被选中以找到替换候选。
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公开(公告)号：US08984227B2
公开(公告)日：2015-03-17
申请号：US13855174
申请日：2013-04-02
Applicant: Apple Inc.
Inventor： Shinye Shiu , Sukalpa Biswas , Wolfgang H. Klingauf , Rong Zhang Hu
CPC classification number: G06F1/3275 , G06F12/0864 , G06F12/123 , G06F12/126 , G06F2212/1028 , G06F2212/601 , Y02D10/13
Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other ways. A target active way count is maintained and the system cache attempts to keep the number of currently active ways equal to the target active way count. The bandwidth and allocation intention of the system cache is monitored. Based on these characteristics, the system cache adjusts the target active way count up or down, which then causes the number of currently active ways to rise or fall in response to the adjustment to the target active way count.
Abstract translation: 用于降低存储器控制器内的系统高速缓存的功耗的方法和装置。 系统缓存包含多种方式，每种方式独立于其他方式供电。 维护目标活动方式计数，并且系统缓存尝试将当前活动方式的数量保持等于目标活动方式计数。 监控系统缓存的带宽和分配意图。 基于这些特征，系统高速缓存调整目标活动方式向上或向下计数，从而响应于对目标活动方式计数的调整，使当前活动方式的数量上升或下降。
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公开(公告)号：US11030102B2
公开(公告)日：2021-06-08
申请号：US16125438
申请日：2018-09-07
Applicant: Apple Inc.
Inventor： Harshavardhan Kaushikkar , Rong Zhang Hu , Xiaoming Wang
IPC: G06F12/0815 , G06F12/0855 , G06F13/16 , G06F13/40
Abstract: Systems, apparatuses, and methods for reducing memory cache control command hops through a fabric are disclosed. A system includes an interconnect fabric, a plurality of transaction processing queues, and a plurality of memory pipelines. Each memory pipeline includes an arbiter, a combined coherence point and memory cache controller unit, and a memory controller coupled to a memory channel. Each combined unit includes a memory cache controller, a memory cache, and a duplicate tag structure. A single arbiter per memory pipeline performs arbitration across the transaction processing queues to select a transaction address to feed the memory pipeline's combined unit. The combined unit performs coherence operations and a memory cache lookup for the selected transaction. Only after processing is completed in the combined unit is the transaction moved out of its transaction processing queue, reducing power consumption caused by data movement through the fabric.
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公开(公告)号：US20200081836A1
公开(公告)日：2020-03-12
申请号：US16125438
申请日：2018-09-07
Applicant: Apple Inc.
Inventor： Harshavardhan Kaushikkar , Rong Zhang Hu , Xiaoming Wang
IPC: G06F12/0815 , G06F12/0855 , G06F13/16 , G06F13/40
Abstract: Systems, apparatuses, and methods for reducing memory cache control command hops through a fabric are disclosed. A system includes an interconnect fabric, a plurality of transaction processing queues, and a plurality of memory pipelines. Each memory pipeline includes an arbiter, a combined coherence point and memory cache controller unit, and a memory controller coupled to a memory channel. Each combined unit includes a memory cache controller, a memory cache, and a duplicate tag structure. A single arbiter per memory pipeline performs arbitration across the transaction processing queues to select a transaction address to feed the memory pipeline's combined unit. The combined unit performs coherence operations and a memory cache lookup for the selected transaction. Only after processing is completed in the combined unit is the transaction moved out of its transaction processing queue, reducing power consumption caused by data movement through the fabric.
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