公开(公告)号：US10802968B2

公开(公告)日：2020-10-13

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/0815 ,  G06F12/0813 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

公开(公告)号：US20150143044A1

公开(公告)日：2015-05-21

申请号：US14081549

申请日：2013-11-15

Applicant: APPLE INC.

Inventor： Manu Gulati ,  Harshavardhan Kaushikkar ,  Gurjeet S. Saund ,  Wei-Han Lien ,  Gerard R. Williams, III ,  Sukalpa Biswas ,  Brian P. Lilly ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/084 ,  G06F12/0802 ,  G06F12/0806 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0822 ,  G06F2212/1028 ,  Y02D10/13

Abstract: Systems, processors, and methods for sharing an agent's private cache with other agents within a SoC. Many agents in the SoC have a private cache in addition to the shared caches and memory of the SoC. If an agent's processor is shut down or operating at less than full capacity, the agent's private cache can be shared with other agents. When a requesting agent generates a memory request and the memory request misses in the memory cache, the memory cache can allocate the memory request in a separate agent's cache rather than allocating the memory request in the memory cache.

Abstract translation: 与SoC中的其他代理程序共享代理的私有缓存的系统，处理器和方法。 SoC中的许多代理除了SoC的共享缓存和内存之外还有一个专用缓存。 如果代理的处理器关闭或以小于满容量运行，代理的私有缓存可以与其他代理共享。 当请求代理产生存储器请求并且存储器请求丢失在存储器高速缓存中时，存储器高速缓存可以在单独的代理的高速缓存中分配存储器请求，而不是在存储器高速缓存中分配存储器请求。

公开(公告)号：US08977817B2

公开(公告)日：2015-03-10

申请号：US13629894

申请日：2012-09-28

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu

IPC: G06F12/08 ,  G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0802 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations.

Abstract translation: 用于减少存储器控制器内的系统高速缓存中的泄漏功率的方法和装置。 系统缓存分为多个小部分，每个部分都由独立可控的电源供电。 当一个部分没有被访问时，提供给该部分的电压降低到足以保留数据但不能访问的电压。 根据目标系统缓存的哪个部分将传入请求分组在一起。 当针对给定部分的足够的请求已经累积时，提供给给定部分的电压增加到足以进行访问的电压。 然后，一旦给定的部分有足够的时间在较高的电压下升高和稳定，等待的请求可以在一连串的操作中访问给定的部分。

公开(公告)号：US20140337649A1

公开(公告)日：2014-11-13

申请号：US13890306

申请日：2013-05-09

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Pulkit Desai ,  Rong Zhang Hu

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

公开(公告)号：US09396122B2

公开(公告)日：2016-07-19

申请号：US13866282

申请日：2013-04-19

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Wolfgang H. Klingauf ,  Rong Zhang Hu ,  Shinye Shiu

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/12 ,  G06F1/32 ,  G09G5/395

CPC classification number: G06F12/0871 ,  G06F1/3218 ,  G06F1/3275 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/122 ,  G06F2212/1028 ,  G06F2212/171 ,  G06F2212/6046 ,  G09G5/395 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/121 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.

Abstract translation: 针对浏览应用程序优化的缓存分配方案的方法和系统。 存储器控制器包括用于减少访问片外存储器的请求数量的存储器高速缓存。 当检测到空闲屏幕使用情况时，使用顺序分配模式将帧缓冲器分配给存储器高速缓存。 以依次方式将像素分配给给定方式的索引，然后以顺序的方式访问各种方式。 当访问给定的方式时，存储器高速缓存的其他方式进入保留模式以减少泄漏功率。

公开(公告)号：US09135177B2

公开(公告)日：2015-09-15

申请号：US13777777

申请日：2013-02-26

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu

IPC: G06F12/00 ,  G06F12/08 ,  G06F13/16

CPC classification number: G06F12/084 ,  G06F12/0859 ,  G06F13/16 ,  G06F2212/304

Abstract: Techniques for escalating a real time agent's request that has an address conflict with a best effort agent's request. A best effort request can be allocated in a memory controller cache but can progress slowly in the memory system due to its low priority. Therefore, when a real time request has an address conflict with an older best effort request, the best effort request can be escalated if it is still pending when the real time request is received at the memory controller cache. Escalating the best effort request can include setting the push attribute of the best effort request or sending another request with a push attribute to bypass or push the best effort request.

Abstract translation: 用于升级具有与尽力而为代理人请求相关的地址的实时代理请求的技术。 可以在存储器控制器高速缓存中分配尽力而为的请求，但是由于其优先级低，可以缓慢地在存储器系统中进行。 因此，当实时请求具有与较早的最佳努力请求相冲突的地址时，如果在存储器控制器高速缓存处接收到实时请求时仍然处于待命状态，则尽力而为请求可以被升级。 提升尽力而为的请求可以包括设置尽力而为请求的推送属性或者使用推送属性发送另一个请求来绕过或推送尽力而为的请求。

公开(公告)号：US20140317355A1

公开(公告)日：2014-10-23

申请号：US13866282

申请日：2013-04-19

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Wolfgang H. Klingauf ,  Rong Zhang Hu ,  Shinye Shiu

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0871 ,  G06F1/3218 ,  G06F1/3275 ,  G06F12/0864 ,  G06F12/0893 ,  G06F12/122 ,  G06F2212/1028 ,  G06F2212/171 ,  G06F2212/6046 ,  G09G5/395 ,  G09G2330/021 ,  G09G2330/022 ,  G09G2360/121 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and systems for cache allocation schemes optimized for browsing applications. A memory controller includes a memory cache for reducing the number of requests that access off-chip memory. When an idle screen use case is detected, the frame buffer is allocated to the memory cache using a sequential allocation mode. Pixels are allocated to indexes of a given way in a sequential fashion, and then each way is accessed in a sequential fashion. When a given way is being accessed, the other ways of the memory cache are put into retention mode to reduce the leakage power.

Abstract translation: 针对浏览应用程序优化的缓存分配方案的方法和系统。 存储器控制器包括用于减少访问片外存储器的请求数量的存储器高速缓存。 当检测到空闲屏幕使用情况时，使用顺序分配模式将帧缓冲器分配给存储器高速缓存。 以依次方式将像素分配给给定方式的索引，然后以顺序的方式访问各种方式。 当访问给定的方式时，存储器高速缓存的其他方式进入保留模式以减少泄漏功率。

公开(公告)号：US09400544B2

公开(公告)日：2016-07-26

申请号：US13855189

申请日：2013-04-02

Applicant: Apple Inc.

Inventor： Wolfgang H. Klingauf ,  Rong Zhang Hu ,  Sukalpa Biswas ,  Shinye Shiu

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section.

Abstract translation: 用于减少存储器控制器内的系统高速缓存中的泄漏功率的方法和装置。 系统高速缓存分为多个部分，每个部分由两个电源电压之一供电。 当一个部分没有被访问时，提供给该部分的电压降低到足以保留数据但不能访问的电压。 高速缓存利用最大允许的有效部分策略来限制在任何给定时间处于活动状态的部分数量以减少泄漏功率。 每个部分包括相应的空闲定时器和休眠平衡定时器。 空闲定时器跟踪该段已经空闲多久，并且使用休眠定时器来定期将段从唤醒模式唤醒，以检查是否有一个针对该段的挂起请求。

公开(公告)号：US20140310469A1

公开(公告)日：2014-10-16

申请号：US13860885

申请日：2013-04-11

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Harshavardhan Kaushikkar ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G06F2212/1008 ,  G06F2212/507

Abstract: An apparatus for processing coherency transactions in a computing system is disclosed. The apparatus may include a request queue circuit, a duplicate tag circuit, and a memory interface unit. The request queue circuit may be configured to generate a speculative read request dependent upon a received read transaction. The duplicate tag circuit may be configured to store copies of tag from one or more cache memories, and to generate a kill message in response to a determination that data requested in the received read transaction is stored in a cache memory. The memory interface unit may be configured to store the generated speculative read request dependent upon a stall condition. The stored speculative read request may be sent to a memory controller dependent upon the stall condition. The memory interface unit may be further configured to delete the speculative read request in response to the kill message.

Abstract translation: 公开了一种用于处理计算系统中的一致性事务的装置。 该装置可以包括请求队列电路，复制标签电路和存储器接口单元。 请求队列电路可以被配置为根据所接收的读取事务来生成推测性读取请求。 重复标签电路可以被配置为存储来自一个或多个高速缓冲存储器的标签的副本，并且响应于在所接收的读事务中请求的数据被存储在高速缓冲存储器中的确定来生成杀死消息。 存储器接口单元可以被配置为根据失速条件来存储产生的推测性读取请求。 存储的推测性读取请求可以根据失速条件发送到存储器控制器。 存储器接口单元还可以被配置为响应于杀死消息来删除推测性读取请求。

公开(公告)号：US20140298058A1

公开(公告)日：2014-10-02

申请号：US13855189

申请日：2013-04-02

Applicant: APPLE INC.

Inventor： Wolfgang H. Klingauf ,  Rong Zhang Hu ,  Sukalpa Biswas ,  Shinye Shiu

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3296 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/172 ,  Y02D50/20

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple sections, and each section is supplied with power from one of two supply voltages. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. The cache utilizes a maximum allowed active section policy to limit the number of sections that are active at any given time to reduce leakage power. Each section includes a corresponding idle timer and break-even timer. The idle timer keeps track of how long the section has been idle and the break-even timer is used to periodically wake the section up from retention mode to check if there is a pending request that targets the section.

Abstract translation: 用于减少存储器控制器内的系统高速缓存中的泄漏功率的方法和装置。 系统高速缓存分为多个部分，每个部分由两个电源电压之一供电。 当一个部分没有被访问时，提供给该部分的电压降低到足以保留数据但不能访问的电压。 高速缓存利用最大允许的有效部分策略来限制在任何给定时间处于活动状态的部分数量以减少泄漏功率。 每个部分包括相应的空闲定时器和休眠平衡定时器。 空闲定时器跟踪该段已经空闲多久，并且使用休眠定时器来定期将段从唤醒模式唤醒，以检查是否有一个针对该段的挂起请求。