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公开(公告)号：US20170140736A1
公开(公告)日：2017-05-18
申请号：US15350894
申请日：2016-11-14
Applicant: ARM Limited
Inventor： Daren Croxford , Damian Piotr Modrzyk , Piotr Tadeusz Chrobak
Abstract: A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.
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公开(公告)号：US10825423B2
公开(公告)日：2020-11-03
申请号：US16667658
申请日：2019-10-29
Applicant: Arm Limited
Inventor： Daren Croxford , Damian Piotr Modrzyk , Piotr Tadeusz Chrobak
Abstract: A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.
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公开(公告)号：US10649795B2
公开(公告)日：2020-05-12
申请号：US15531981
申请日：2015-11-30
Applicant: ARM Limited
Inventor： Daren Croxford , Piotr Tadeusz Chrobak , Damian Piotr Modrzyk
Abstract: An apparatus for compositing an output surface (10) from a plurality of input surfaces (1, 2, 3, 4) includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor. When it is determined that two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor, the processing circuitry is configured to provide data representing the secondary surface to the composition processor, the data indicating the input surfaces that contribute to the secondary surface.
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公开(公告)号：US10510324B2
公开(公告)日：2019-12-17
申请号：US15350894
申请日：2016-11-14
Applicant: ARM Limited
Inventor： Daren Croxford , Damian Piotr Modrzyk , Piotr Tadeusz Chrobak
Abstract: A display controller 12 comprises a first display processing core 20 comprising a first input stage 21 operable to read at least one input surface, a first processing stage operable to process one or more input surfaces to generate an output surface, and a first output stage 26 operable to provide an output surface for display to a first display 6, and a second display processing core 40 comprising a second input stage 41 operable to read at least one input surface, a second processing stage operable to process one or more input surfaces to generate an output surface, and a second output stage 46 operable to provide an output surface for display to a second display 8. The display controller 12 also comprises an internal data path 30 for passing pixel data of an output surface from the second display core 40 to the first display core 20.
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公开(公告)号：US20170329613A1
公开(公告)日：2017-11-16
申请号：US15531981
申请日：2015-11-30
Applicant: ARM Limited
Inventor： Daren Croxford , Piotr Tadeusz Chrobak , Damian Piotr Modrzyk
CPC classification number: G06F9/451 , G09G5/14 , G09G5/377 , G09G2340/02 , G09G2360/08 , G09G2360/121
Abstract: An apparatus for compositing an output surface (10) from a plurality of input surfaces (1, 2, 3, 4) includes processing circuitry and a composition processor. The processing circuitry is configured to determine whether two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor. When it is determined that two or more input surfaces of the plurality of input surfaces (1, 2, 3, 4) can be combined into a single secondary surface for provision to the composition processor, the processing circuitry is configured to provide data representing the secondary surface to the composition processor, the data indicating the input surfaces that contribute to the secondary surface.
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Patent Agency Ranking
公开(公告)号：US20170162179A1
公开(公告)日：2017-06-08
申请号：US15361751
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Michal Karol Bogusz , Damian Piotr Modrzyk , Quinn Carter , Thomas James Cooksey
IPC: G09G5/397 , G09G5/36 , G06F12/1027 , G06F12/0862 , G06F12/0875
Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.
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公开(公告)号：US20250036485A1
公开(公告)日：2025-01-30
申请号：US18782668
申请日：2024-07-24
Applicant: Arm Limited
Inventor： Balaji Venu , Metin Gokhan Ünal , Giacomo Gabrielli , Damian Piotr Modrzyk , Dino Santoro
IPC: G06F9/52
Abstract: Provided is a data stream processor comprising: a configurable compute unit comprising plural processing units each configured to receive at least one portion of input data and process the at least one portion of a repetitive arithmetical/logical operation on the data; an input memory unit in electronic communication with the configurable compute unit and configured to supply at least one portion of the input data to at least one of the plural processing units in the configurable compute unit; and at least one accumulator unit in electronic communication with the configurable compute unit and configured to receive at least two portions of processed data from the configurable compute unit and to output accumulated data; wherein each of the plural processing units is further configured to forward its processed data to a next processing unit and/or to an accumulator unit.
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公开(公告)号：US11301973B2
公开(公告)日：2022-04-12
申请号：US16834847
申请日：2020-03-30
Applicant: Arm Limited , Apical Limited
Inventor： Brian Paul Starkey , Damian Piotr Modrzyk , Güney Kayim , Lukas Krasula
Abstract: A method of performing tone mapping in a stream of images (Fr1 . . . N) includes, for each image (FrN) in the stream: sparsely reading image data values (IDN) corresponding to the image (FrN) to provide sparse image data from a plurality of sparsely distributed positions (Pos1 . . . k) in the image (FrN); generating, based on the sparse image data, tone mapping parameters of a tone mapping algorithm (TMA) for each position in the image (FrN); each position in the image (FrN) including the sparsely distributed positions (Pos1 . . . k) and a plurality of further positions (PosF1 . . . j) in the image (FrN); reading the image data values (IDN) corresponding to the image (FrN) to provide image data from each position in the image (FrN); and tone mapping the image by mapping the image data from each position in the image (FrN) to adjusted image data using the generated tone mapping parameters.
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公开(公告)号：US10593305B2
公开(公告)日：2020-03-17
申请号：US15361751
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Michal Karol Bogusz , Damian Piotr Modrzyk , Quinn Carter , Thomas James Cooksey
IPC: G06F12/0862 , G06F12/0875 , G06F12/1027 , G06T1/60 , G09G5/397 , G09G5/36 , G09G5/395 , G06T15/00
Abstract: A display controller for a data processing system includes a memory read sub-system operable to read data of input surfaces to be used as input layers to be processed by the display controller.The memory read sub-system is operable to request in advance the loading of memory address translation data into a memory address translation data cache for memory pages storing data relating to an input surface. The memory read sub-system selects the memory pages that it requests the advance loading of address translation data for based on information relating to the data for the input surface that will be required by the display controller to generate the output surface, such as the vertical and horizontal size of the input layer that the input surface will be used for, an indication of any flipping or rotation of the input surface, etc.
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公开(公告)号：US10394522B2
公开(公告)日：2019-08-27
申请号：US15653456
申请日：2017-07-18
Applicant: ARM Limited
Inventor： Damian Piotr Modrzyk , David Brown , Ozgur Ozkurt
Abstract: A display controller for a data processing system comprises two sets of display processing units, each set of display processing units comprising an input unit operable to read at least one input surface, a processing unit operable to process one or more input surfaces to generate an output surface, and an output unit operable to provide an output surface for display to a display. The display controller also includes internal data path via which pixel data of a surface may be passed between the sets of display processing units, and a control unit that can selectively activate one or both of the sets of display processing units to process one or more input surfaces to generate one or more output surfaces for display.
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