公开(公告)号：US10042640B2

公开(公告)日：2018-08-07

申请号：US15076889

申请日：2016-03-22

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec ,  Cedric Denis Robert Airaud

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/38 ,  G06F9/52 ,  G06F8/41

Abstract: A data processing system 2 includes multiple out-of-order issue queues 8, 10. A master serialization instruction MSI received by a first issue queue 8 is detected by slave generation circuitry 24 which generates a slave serialization instruction SSI added to a second issue queue 10. The master serialization instruction MSI manages serialization relative to the instructions within the first issue queue 8. The slave serialization instruction SSI manages serialization relative to the instructions within the second issue queue 10. The master serialization instruction MSI and the slave serialization instruction SSI are removed when both have met their serialization conditions and are respectively the oldest instructions within their issue queues.

公开(公告)号：US09400655B2

公开(公告)日：2016-07-26

申请号：US13847892

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Cedric Denis Robert Airaud ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract translation: 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。

公开(公告)号：US09170819B2

公开(公告)日：2015-10-27

申请号：US13737137

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Nicolas Chaussade ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Cedric Denis Robert Airaud

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3867 ,  G06F9/30072 ,  G06F9/3826

Abstract: A data processing apparatus comprises first and second processing circuitry. A conditional instruction executed by the second processing circuitry may have an outcome which is dependent on one of a plurality of sets of condition information maintained by the first processing circuitry. A first forwarding path can forward the sets of condition information from the first processing circuitry to a predetermined pipeline stage of a processing pipeline of the second processing circuitry. A request path can transmit a request signal from the second processing circuitry to the first processing circuitry, the request signal indicating a requested set of condition information which was not yet valid when a conditional instruction was at the predetermined pipeline stage. A second forwarding path may forward the requested set of condition information to a subsequent pipeline stage when the information becomes valid.

Abstract translation: 数据处理装置包括第一和第二处理电路。 由第二处理电路执行的条件指令可以具有取决于由第一处理电路维护的多组条件信息之一的结果。 第一转发路径可将来自第一处理电路的条件信息集合转发到第二处理电路的处理流水线的预定流水线级。 请求路径可以将来自第二处理电路的请求信号发送到第一处理电路，该请求信号指示当条件指令处于预定流水线阶段时尚未有效的请求的条件信息集合。 当信息变得有效时，第二转发路径可以将所请求的条件信息集合转发到后续流水线级。

公开(公告)号：US20140181478A1

公开(公告)日：2014-06-26

申请号：US13723974

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Cédric Denis Robert AIRAUD ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30141 ,  G06F9/3857

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier. Write port usage is tracked by a write port usage scoreboard 26 which is both read and updated by the bypass circuitry 22 when re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline 14.

Abstract translation: 在处理流水线14内，发布控制电路12用于在将浮点乘法指令发布到浮点流水线14时仲裁写端口的可用性。如果不是以冲零模式工作，则根据产生的非正规输出操作数 处理可能或可能不需要。 在需要进行异常处理的问题上做出悲观的假设，因此，保留的写入端口是在开始周期之后的第一预定数量的处理周期，以考虑使用异常处理流水线级20。沿着处理流水线14 ，状态变为可用，其指示是否实际需要异常处理。 如果不需要异常处理并且写入端口可用于处理周期之前，则旁路电路22用于绕过异常处理流水线级20，使得输出操作数将被更早地写入一个处理周期的寄存器组16。 写端口使用记录板26由写入端口使用记分板26跟踪，当通过沿管线14传送的浮点乘法指令重新协商写入端口可用性时，旁路电路22读取和更新。

公开(公告)号：US11449642B2

公开(公告)日：2022-09-20

申请号：US17012470

申请日：2020-09-04

Applicant: Arm Limited

Inventor： Carlo Dario Fanara ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F21/75

Abstract: An electronic circuit includes a plurality of processing elements, a register bank, and a control circuit. The processing elements consume power by processing a plurality of operands to generate a plurality of result values. The register bank has a plurality of registers. The control circuit is configured to determine one or more unused processing elements among the processing elements by snooping one or more incoming operands and an instruction type, control routing of one or more random operands from the register bank to the unused processing elements, and control routing of a random result value generated by one of the unused processing elements into a trash register of the registers. The power consumed by the unused processing elements in the generation of the random result value and a write of the random result value into the trash register temporally blurs a total power consumed by the electronic circuit.

公开(公告)号：US10789169B2

公开(公告)日：2020-09-29

申请号：US16018438

申请日：2018-06-26

Applicant: ARM Limited

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Claire Aupetit

IPC: G06F12/08 ,  G06F12/0862 ,  G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for controlling use of a register cache. The apparatus has execution circuitry for executing instructions to process data values, and a register file comprising a plurality of registers in which to store the data values for access by the execution circuitry. A register cache is also provided that has a plurality of entries and is arranged to cache a subset of the data values for access by the execution circuitry. Each entry is arranged to cache a data value and an indication of the register associated with that cached data value. Prefetch circuitry then performs prefetch operations to prefetch data values from the register file into the register cache. Timing indication storage is used to store, for each data value to be generated as a result of instructions being executed within the execution circuitry, a register identifier for that data value, and timing information indicating when that data value will be generated by the execution circuitry. Cache usage control circuitry is then responsive to receipt of a plurality of register identifiers associated with source data values for a pending instruction yet to be executed by the execution circuitry, to generate, with reference to the timing information in the timing indication storage, a timing control signal to control timing of at least one prefetch operation performed by the prefetch circuitry. Such an approach can lead to significant improvements in the efficiency of utilisation of the register cache.

公开(公告)号：US10545764B2

公开(公告)日：2020-01-28

申请号：US15082601

申请日：2016-03-28

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Thomas Gilles Tarridec ,  Cedric Denis Robert Airaud

IPC: G06F9/38

Abstract: A data processing apparatus comprises register rename circuitry for mapping architectural register specifiers specified by instructions to physical registers to be accessed in response to the instructions. Available register control circuitry controls which physical registers are available for mapping to an architectural register specifier by the register rename circuitry. For at least one group of two or more physical registers, the available register control circuitry controls availability of the registers based on a group tracking indication indicative of whether there is at least one pending access to any of the physical registers in the group.

公开(公告)号：US10540299B2

公开(公告)日：2020-01-21

申请号：US15638524

申请日：2017-06-30

Applicant: ARM LIMITED

Inventor： Carlo Dario Fanara ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Jocelyn Francois Orion Jaubert

IPC: G06F9/44 ,  G06F12/14 ,  G06F9/4401 ,  G06F9/24 ,  G06F1/24 ,  G06F9/30

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

公开(公告)号：US09311087B2

公开(公告)日：2016-04-12

申请号：US13724046

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Cédric Denis Robert Airaud ,  Guillaume Schon ,  Frederic Jean Denis Arsanto

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3865

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract translation: 数据处理装置2支持推测执行和使用粘滞位。 粘性位的不同版本与推测程序流的每个段相关联。 节目流的片段由对应于节目指令的推测节点分开，节目指令可以跟随作为下一节目指令的多个不同的备选节目指令。 当一个猜测节点被解析时，由该推测节点分隔的段被合并，并且这两个段的粘滞位值被合并。

公开(公告)号：US20140181485A1

公开(公告)日：2014-06-26

申请号：US13724046

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Cédric Denis Robert Airaud ,  Guillaume Schon ,  Frederic Jean Denis Arsanto

IPC: G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3865

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract translation: 数据处理装置2支持推测执行和使用粘滞位。 粘性位的不同版本与推测程序流的每个段相关联。 节目流的片段由对应于节目指令的推测节点分开，节目指令可以跟随作为下一节目指令的多个不同的备选节目指令。 当一个猜测节点被解析时，由该推测节点分隔的段被合并，并且这两个段的粘滞位值被合并。