公开(公告)号：US10902113B2

公开(公告)日：2021-01-26

申请号：US15793186

申请日：2017-10-25

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Frederic Jean Denis Arsanto ,  Carlo Dario Fanara ,  Jocelyn François Orion Jaubert

IPC: H04L29/06 ,  G06F21/55 ,  G06F9/30 ,  G06F21/75 ,  G06F11/30

Abstract: Data processing circuitry comprises a set of two or more computational units to perform respective computational operations; an instruction decoder to decode successive data processing instructions and, for a given data processing instruction, to control one or more of the computational units to perform those computational operations required to execute the given data processing instruction; and control circuitry responsive to the given data processing instruction, to control one or more others of the computational units to perform further computational operations, other than the computational operations required to execute the given data processing instruction, during execution of the given data processing instruction.

公开(公告)号：US10572262B2

公开(公告)日：2020-02-25

申请号：US15651158

申请日：2017-07-17

Applicant: ARM LIMITED

Inventor： Jocelyn Francois Orion Jaubert ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Carlo Dario Fanara

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises a set of registers and mapping circuitry to perform a mapping operation to map each of a set of register specifiers to a respective register from among the set of registers in dependence on a mapping function. The mapping function is dependent on a key value. In addition, the mapping for at least two register specifiers from among the set of register specifiers is dependent on the same key value.

公开(公告)号：US09424045B2

公开(公告)日：2016-08-23

申请号：US13752621

申请日：2013-01-29

Applicant: ARM LIMITED

Inventor： Cedric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Frederic Claude Marie Piry ,  Albin Pierick Tonnerre

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/345 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30014 ,  G06F9/30196

Abstract: An apparatus and method includes execution circuitry including a wide operand execution unit configured to allow up to N bits of operand data to be processed during execution of a single instruction. Decoder circuitry decodes and generates, for each instruction, at least one control data block identifying an operation to be performed by the execution circuitry and at least two re-combineable control data blocks for the instruction. Issue queue control circuitry then allocates a slot in the issue queue for each of the at least two data blocks and up to M bits of associated operand data, and marks those allocated slots to identify that they contain re-combineable control data blocks. The issue queue control circuitry issues the combined block to said wide operand execution unit along with the operand data contained in each of the allocated slots for said at least two control data blocks.

Abstract translation: 一种装置和方法包括执行电路，其包括宽操作数执行单元，其被配置为允许在单个指令的执行期间处理最多N位的操作数数据。 解码器电路针对每个指令对至少一个控制数据块进行解码并生成至少一个控制数据块，该控制数据块标识由执行电路执行的操作和用于该指令的至少两个可重新组合的控制数据块。 发出队列控制电路然后为发送队列中的每个至少两个数据块和相关操作数数据的高达M位分配一个时隙，并标记这些分配的时隙以标识它们包含可重新组合的控制数据块。 所述问题队列控制电路与包含在所述至少两个控制数据块的所分配的时隙中的操作数数据一起向所述宽操作数执行单元发出组合块。

公开(公告)号：US09286069B2

公开(公告)日：2016-03-15

申请号：US13723974

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Cédric Denis Robert Airaud ,  Luca Scalabrino ,  Frederic Jean Denis Arsanto ,  Guillaume Schon

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30141 ,  G06F9/3857

Abstract: Within a processing pipeline 14, issue control circuitry 12 serves to arbitrate write port availability when floating point multiplication instructions are issued into a floating point pipeline 14. If not operating in a flush-to-zero mode, then depending upon the output operands generated denormal handling may or may not be required. A pessimistic assumption is made upon issue that denormal handling will be required and accordingly the write port reserved is a first predetermined number of processing cycles after the start cycle to take account of use of the denormal handling pipeline stage 20. Partway along the processing pipeline 14, state becomes available which indicates whether or not denormal handling is actually required. If denormal handling is not required and a write port is available one processing cycle earlier, then bypass circuitry 22 serves to bypass the denormal handling pipeline stage 20 such that the output operand will be written to the register bank 16 one processing cycle earlier. Write port usage is tracked by a write port usage scoreboard 26 which is both read and updated by the bypass circuitry 22 when re-arbitrating write port availability partway through a floating point multiplication instruction passing along the pipeline 14.

Abstract translation: 在处理流水线14内，发布控制电路12用于在将浮点乘法指令发布到浮点流水线14时仲裁写端口的可用性。如果不是以冲零模式运行，则根据产生的非正规输出操作数 处理可能或可能不需要。 在需要进行异常处理的问题上做出悲观的假设，因此，保留的写入端口是在开始周期之后的第一预定数量的处理周期，以考虑使用异常处理流水线级20。沿着处理流水线14 ，状态变为可用，其指示是否实际需要异常处理。 如果不需要异常处理并且写入端口可用于处理周期之前，则旁路电路22用于绕过异常处理流水线级20，使得输出操作数将被更早地写入一个处理周期的寄存器组16。 写端口使用记录板26由写入端口使用记分板26跟踪，当通过沿管线14传送的浮点乘法指令重新协商写入端口可用性时，旁路电路22读取和更新。

公开(公告)号：US10540299B2

公开(公告)日：2020-01-21

申请号：US15638524

申请日：2017-06-30

Applicant: ARM LIMITED

Inventor： Carlo Dario Fanara ,  Frederic Jean Denis Arsanto ,  Guillaume Schon ,  Jocelyn Francois Orion Jaubert

IPC: G06F9/44 ,  G06F12/14 ,  G06F9/4401 ,  G06F9/24 ,  G06F1/24 ,  G06F9/30

Abstract: An apparatus has processing circuitry to perform data processing in one of two or more operating states associated with different levels of privilege. At least one operating state holding element holds a state indication indicating a current operating state of the processing circuitry. In response to a transition of a reset signal from a first value to a second value for triggering a reset of the processing circuitry, the at least one operating state holding element resets the state indication to indicate a default operating state other than a most privileged operating state of the two or more operating states.

公开(公告)号：US09361111B2

公开(公告)日：2016-06-07

申请号：US13737153

申请日：2013-01-09

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Melanie Emanuelle Lucie Teyssier ,  Cedric Denis Robert Airaud ,  Guillaume Schon

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3842 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3885

Abstract: First processing circuitry processes at least part of a stream of program instructions. The first processing circuitry has registers for storing data and register renaming circuitry for mapping architectural register specifiers to physical register specifiers. A renaming data store stores renaming entries for identifying a register mapping between the architectural and physical register specifiers. At least some renaming entries have a count value indicating a number of speculation points occurring between generation of a previous count value and generation of the count value. The speculation points may for example be branch operation or load/store operations.

Abstract translation: 第一处理电路处理程序指令流的至少一部分。 第一处理电路具有用于存储用于将体系结构寄存器说明符映射到物理寄存器说明符的数据和寄存器重命名电路的寄存器。 重命名数据存储存储用于识别架构和物理寄存器说明符之间的寄存器映射的重命名条目。 至少一些重命名条目具有指示在生成先前计数值和生成计数值之间发生的推测点数的计数值。 推测点可以例如是分支操作或加载/存储操作。

公开(公告)号：US09311087B2

公开(公告)日：2016-04-12

申请号：US13724046

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Luca Scalabrino ,  Cédric Denis Robert Airaud ,  Guillaume Schon ,  Frederic Jean Denis Arsanto

IPC: G06F15/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3865

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract translation: 数据处理装置2支持推测执行和使用粘滞位。 粘性位的不同版本与推测程序流的每个段相关联。 节目流的片段由对应于节目指令的推测节点分开，节目指令可以跟随作为下一节目指令的多个不同的备选节目指令。 当一个猜测节点被解析时，由该推测节点分隔的段被合并，并且这两个段的粘滞位值被合并。

公开(公告)号：US20140181485A1

公开(公告)日：2014-06-26

申请号：US13724046

申请日：2012-12-21

Applicant: ARM LIMITED

Inventor： Luca SCALABRINO ,  Cédric Denis Robert Airaud ,  Guillaume Schon ,  Frederic Jean Denis Arsanto

IPC: G06F9/38

CPC classification number: G06F9/30087 ,  G06F9/3804 ,  G06F9/3842 ,  G06F9/3865

Abstract: A data processing apparatus 2 supports speculative execution and the use of sticky bits. A different version of a sticky bit is associated with each segment of the speculative program flow. The segments of the program flow are separated by speculation nodes corresponding to program instructions which may be followed by a plurality of different alternative program instruction serving as the next program instruction. When a speculation node is resolved, then the segments separated by that speculation node are merged and the sticky bit values for those two segments are merged.

Abstract translation: 数据处理装置2支持推测执行和使用粘滞位。 粘性位的不同版本与推测程序流的每个段相关联。 节目流的片段由对应于节目指令的推测节点分开，节目指令可以跟随作为下一节目指令的多个不同的备选节目指令。 当一个猜测节点被解析时，由该推测节点分隔的段被合并，并且这两个段的粘滞位值被合并。

公开(公告)号：US10445500B2

公开(公告)日：2019-10-15

申请号：US15635614

申请日：2017-06-28

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Frederic Jean Denis Arsanto ,  Jocelyn François Orion Jaubert ,  Carlo Dario Fanara

IPC: G06F21/56 ,  G06F3/06 ,  G06F21/62 ,  G06F21/78 ,  G06F21/57

Abstract: An apparatus has a number of data holding elements for holding data values which are reset to a reset value in response to a transition of a signal at a reset signal input of the data holding element from a first value to a second value. A reset tree is provided to distribute a reset signal received at root node of the reset tree to the reset signal inputs of the data holding elements. At least one reset attack detection element is provided, with its reset signal input coupled to a given node of the reset tree, to assert an error signal when its reset signal input transitions from the first value to a second value. Reset error clearing circuitry triggers clearing of the error signal, when the reset signal at the root node of the reset tree transitions from the second value to the first value.

公开(公告)号：US09400655B2

公开(公告)日：2016-07-26

申请号：US13847892

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Guillaume Schon ,  Cedric Denis Robert Airaud ,  Frederic Jean Denis Arsanto ,  Luca Scalabrino

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3017 ,  G06F9/30098 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3863

Abstract: Register renaming circuitry for a processing apparatus configured to process a stream of instructions from an instruction set specifying registers from an architectural set of registers. The apparatus including a physical set of registers configured to store data values being processed by the processing apparatus. Register renaming circuitry is configured to receive a stream of operations from an instruction decoder and to map registers that are to be written to by the stream of operations to physical registers within the physical set of registers that are currently available. The register renaming circuitry comprises register release circuitry configured to release the physical registers that have been mapped to the registers when a first set of conditions have been met, and to release the physical registers that have been mapped to the additional registers when a second set of conditions have been met.

Abstract translation: 用于处理装置的注册重命名电路，被配置为处理来自指定集合的​​指令集的指令流，所述指令集指定来自架构的一组寄存器。 该装置包括被配置为存储由处理装置处理的数据值的寄存器的物理组。 寄存器重命名电路被配置为从指令解码器接收操作流，并将要由操作流写入的寄存器映射到当前可用的寄存器的物理组内的物理寄存器。 寄存器重命名电路包括寄存器释放电路，其被配置为当满足第一组条件时释放已经被映射到寄存器的物理寄存器，并且当第二组存储器被释放时已被映射到附加寄存器的物理寄存器 条件得到满足。