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公开(公告)号：US11307855B2
公开(公告)日：2022-04-19
申请号：US17096014
申请日：2020-11-12
Applicant: Arm Limited
Inventor： John Michael Horley , Simon John Craske
IPC: G06F9/30
Abstract: Instructions have an opcode and at least one data operand, the opcode identifying a data processing operation to perform on the at least one data operand. For a register-provided-opcode instruction specifying at least one source register, at least part of the opcode is a register-provided opcode represented by a first portion of data stored in said at least one source register of the register-provided-opcode instruction, and the at least one data operand comprises data represented by a second portion of the data stored in the at least one source register. The register-provided opcode is used to select between different data processing operations supported for the same instruction encoding of the register-provided-opcode instruction.
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12.发明授权公开(公告)号：US11048617B2
公开(公告)日：2021-06-29
申请号：US16971415
申请日：2019-01-17
Applicant: Arm Limited
Inventor： Michael John Williams , Graeme Peter Barnes , John Michael Horley
IPC: G06F11/36
Abstract: A technique is provided for accessing metadata when debugging a program to be executed on processing circuitry. The processing circuitry operates on data formed of data granules having associated metadata items. A method of operating a debugger is provided that comprises controlling the performance of metadata access operations when the debugger decides to access a specified number of metadata items. In particular, the specified number is such that the metadata access operation needs to be performed by the processing circuitry multiple times in order to access the specified number of metadata items. Upon deciding to access a specified number of metadata items, the debugger issues at least one command to cause the processing circuitry to perform a plurality of instances of the metadata access operation in order to access at least a subset of the specified number of metadata items. The number of metadata items accessed by each instance of the metadata access operation is non-deterministic by the debugger from the metadata access operation. However, the at least one command is such that the plurality of instances of the metadata access operation are performed by the processing circuitry without the debugger interrogating the processing circuitry between each instance of the metadata access operation to determine progress in the number of metadata items accessed. Such an approach can significantly improve the efficiency of performing such accesses to metadata items under debugger control.
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公开(公告)号：US11036616B2
公开(公告)日：2021-06-15
申请号：US15008569
申请日：2016-01-28
Applicant: ARM LIMITED
Inventor： Michael John Williams , John Michael Horley
Abstract: An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.
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公开(公告)号：US20180210805A1
公开(公告)日：2018-07-26
申请号：US15838615
申请日：2017-12-12
Applicant: ARM Limited
CPC classification number: G06F11/3466 , G06F7/548 , G06F9/3001 , G06F9/30018 , G06F9/30036 , G06F9/30043 , G06F11/141 , G06F11/3471 , G06F11/3476
Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. The sequence includes at least one predicated vector memory access instruction executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. The vector comprises a plurality of lanes, where the number of lanes is dependent on the size of the data values represented within the vector, and predicate information referenced when executing the predicated vector memory access instruction is used to determine which lanes are subjected to the memory transfer operation. The apparatus has trace generation circuitry to generate from the execution information a data trace stream comprising a plurality of trace elements. For each predicated vector memory access instruction executed, the trace generation circuitry is arranged to issue within the data trace stream a number of address trace elements, each address trace element providing an address indication for an address accessed in memory, and each address trace element being associated with a fixed sized data block irrespective of the size of the data values accessed when executing the memory access instruction. The trace generation circuitry further issues within the data trace stream, for each predicated vector memory access instruction executed, at least one predicate trace element to identify any lanes of the vector that have been omitted from the memory transfer operation. It has been found that such an approach provides a particularly bandwidth efficient mechanism for tracing predicated vector memory access instructions.
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15.发明授权Generating trace data including a lockup identifier indicating occurrence of a lockup state 有权产生跟踪数据，包括指示发生锁定状态的锁定标识符公开(公告)号：US09361204B2
公开(公告)日：2016-06-07
申请号：US13769992
申请日：2013-02-19
Applicant: ARM LIMITED
Inventor： John Michael Horley
CPC classification number: G06F11/348 , G06F11/3466 , G06F11/3476 , G06F11/3636
Abstract: A data processing apparatus has processing circuitry for executing program instructions and trace circuitry for generating trace data indicating processing activities of the processing circuitry. The trace circuitry may detect a lockup state of the processing circuitry in which the processing circuitry does not make forward progress of execution of the program instructions. In response to detecting the lockup state, the trace circuitry may include in the trace data a lockup identifier indicating that the lockup state has occurred.
Abstract translation: 数据处理装置具有用于执行程序指令和跟踪电路的处理电路，用于产生指示处理电路的处理活动的跟踪数据。 跟踪电路可以检测处理电路的锁定状态，其中处理电路不会执行程序指令的执行进度。 响应于检测到锁定状态，跟踪电路可以在跟踪数据中包括指示发生锁定状态的锁定标识符。
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Patent Agency Ranking
公开(公告)号：US12204906B2
公开(公告)日：2025-01-21
申请号：US17999167
申请日：2021-05-20
Applicant: Arm Limited
Inventor： Michael John Williams , Alasdair Grant , John Michael Horley
Abstract: Processing circuitry performs data processing operations in response to instructions fetched from a cache or memory or micro-operations decoded from the instructions. Sampling circuitry selects a subset of instructions or micro-operations as sampled operations to be profiled. Profiling circuitry captures, in response to processing of an instruction or micro-operation selected as a sampled operation, a sample record specifying an operation type of the sampled operation and information about behaviour of the sampled operation which is directly attributed to the sampled operation. The profiling circuitry can include, in the sample record for a sampled operation corresponding to a given instruction, a reference instruction address indicator indicative of an address of a reference instruction appearing earlier or later in program order than the given instruction, for which control flow is sequential between any instructions occurring between the reference instruction and the given instruction in program order.
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公开(公告)号：US12045154B2
公开(公告)日：2024-07-23
申请号：US17998299
申请日：2021-05-13
Applicant: Arm Limited
Inventor： John Michael Horley , Michael John Williams , Mark Salling Rutland , Alasdair Grant
CPC classification number: G06F11/3466 , G06F9/3867 , G06F11/34 , G06F11/3636 , G06F9/3861 , G06F9/3865 , G06F2201/86 , G06F2201/865
Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.
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公开(公告)号：US11561882B2
公开(公告)日：2023-01-24
申请号：US16332130
申请日：2017-08-09
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams , Michael John Gibbs
Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of instruction execution by processing circuitry. An apparatus has an input interface for receiving instruction execution information from the processing circuitry indicative of a sequence of instructions executed by the processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream comprising a plurality of trace elements indicative of execution by the processing circuitry of instruction flow changing instructions within the sequence. The sequence may include a branch behaviour setting instruction that indicates an identified instruction within the sequence, where execution of the branch behaviour setting instruction enables a branch behaviour to be associated with the identified instruction that causes the processing circuitry to branch to a target address identified by the branch behaviour setting instruction when the identified instruction is encountered in the sequence. The trace generation circuitry is further arranged to generate, from the instruction execution information, a trace element indicative of execution behaviour of the branch behaviour setting instruction, and a trace element to indicate that the branch behaviour has been triggered on encountering the identified instruction within the sequence. This enables a very efficient form of trace stream to be used even in situations where the instruction sequence executed by the processing circuitry includes such branch behaviour setting instructions.
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19.发明授权公开(公告)号：US11294787B2
公开(公告)日：2022-04-05
申请号：US16321503
申请日：2017-08-10
Applicant: ARM LIMITED
Inventor： François Christopher Jacques Botman , Thomas Christopher Grocutt , John Michael Horley , Michael John Williams
Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being notified to the trigger signal generation circuitry. This allows the monitoring of particular program instruction execution behaviour to be qualified so that the processing circuitry is only notified if in addition a qualifying event is determined to be present.
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公开(公告)号：US11068270B2
公开(公告)日：2021-07-20
申请号：US16309620
申请日：2016-09-13
Applicant: ARM LIMITED
Inventor： Michael John Gibbs , John Michael Horley
Abstract: An apparatus has an input interface for receiving instruction execution information from processing circuitry, and trace generation circuitry for generating from the instruction execution information a trace stream. The instruction sequence from the processing circuitry includes at least one branch-future instruction that effectively turns an instruction identified by the branch-future instruction into a branch, and in particular causes the processing circuitry to branch to a target address identified by the branch-future instruction when that identified instruction is encountered within the instruction sequence. A branch control cache is used to store branch control information derived from the branch-future instruction, and the trace generation circuitry is arranged to detect, based on that branch control information, when the identified instruction has been encountered by the processing circuitry, and upon such detection to then issue within the trace stream a trace element to indicate that a branch to the target address has occurred.
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