公开(公告)号：US11194693B2

公开(公告)日：2021-12-07

申请号：US15711028

申请日：2017-09-21

Applicant: ARM LIMITED

Inventor： Anitha Kona ,  Michael John Williams ,  John Michael Horley ,  Alasdair Grant

IPC: G06F11/34

Abstract: A data processing apparatus is provided that includes monitor circuitry to produce local trace data indicating behaviour of the data processing apparatus. Interface circuitry communicates with a second data processing apparatus and encoding circuitry produces an encoded instruction to cause the local trace data to be stored in storage circuitry of the second data processing apparatus or to be output at output circuitry of the second data processing apparatus. The interface circuitry transmits the encoded instruction to the second data processing apparatus.

公开(公告)号：US10763829B2

公开(公告)日：2020-09-01

申请号：US15683962

申请日：2017-08-23

Applicant: ARM LIMITED

Inventor： Ashley John Crawford ,  John Michael Horley

IPC: H03J7/06 ,  H03K21/40 ,  G07C3/04 ,  G06F1/3203 ,  H03B5/12 ,  H03K9/06

Abstract: Apparatus comprises master counter circuitry to generate a master count signal in response to a clock signal; slave counter circuitry responsive to the clock signal to generate a respective slave count signal; and a synchronisation connection providing signal communication between the master counter circuitry and the slave counter circuitry; the master counter circuitry being configured to provide to the slave counter circuitry via the synchronisation connection: (i) data indicative of a count offset value and (ii) a timing signal defining a timing relationship between the clock signal and the count offset value; and the slave counter circuitry being configured, during a synchronisation operation for that slave counter circuitry, to initialise a counting operation of that slave counter circuitry in response to the data indicative of the count offset value and a timing signal provided by the master counter circuitry.

公开(公告)号：US20190171511A1

公开(公告)日：2019-06-06

申请号：US15830380

申请日：2017-12-04

Applicant: Arm Limited

Inventor： Anitha KONA ,  Michael John Williams ,  John Michael Horley ,  Alasdair Grant

IPC: G06F11/07 ,  G06F13/42

Abstract: An apparatus includes processor circuitry to perform data processing operations. Interface circuitry forms a connection to a plurality of other apparatuses and receives a foreign exception message indicative of a foreign exception event having been triggered on one of the other apparatuses. In response to receiving the foreign exception message, the interface circuitry forwards the foreign exception message to a set of the plurality of other apparatuses.

公开(公告)号：US12099445B2

公开(公告)日：2024-09-24

申请号：US18320407

申请日：2023-05-19

Applicant: Arm Limited

Inventor： Michael John Williams ,  John Michael Horley

IPC: G06F12/0815

CPC classification number: G06F12/0815

Abstract: Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.

公开(公告)号：US11436124B2

公开(公告)日：2022-09-06

申请号：US16966981

申请日：2019-01-17

Applicant: Arm Limited

Inventor： Michael John Williams ,  John Michael Horley

IPC: G06F11/36 ,  G06F11/14 ,  G06F11/30 ,  G06F13/40 ,  G06F13/42

Abstract: To access metadata when debugging a device, debug access port circuitry including a debug interface receives commands from a debugger, and a bus interface coupled to a bus enables the debugger to access a memory system of the device. The device operates on data granules having associated metadata items, and the bus interface enables communication of both the data granules and the metadata items over the bus. The debug access port circuitry has storage elements accessible via the commands issued from the debugger, such that the accesses performed within the memory system via the bus interface are controlled in dependence on the storage elements accessed by the commands. A metadata storage element stores metadata items, and the debug access port circuitry is responsive to a command from the debugger to perform a memory direct access to transfer metadata items between the metadata storage element and the memory system.

公开(公告)号：US10776120B2

公开(公告)日：2020-09-15

申请号：US15555239

申请日：2016-02-11

Applicant: ARM LIMITED

Inventor： Michael John Williams ,  John Michael Horley ,  Stephan Diestelhorst ,  Richard Roy Grisenthwaite

IPC: G06F9/46 ,  G06F9/52 ,  G06F9/38 ,  G06F11/36 ,  G06F11/34 ,  G06F11/30

Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.

公开(公告)号：US10379989B2

公开(公告)日：2019-08-13

申请号：US13968991

申请日：2013-08-16

Applicant: ARM Limited

Inventor： John Michael Horley ,  Simon John Craske ,  Michael John Gibbs ,  Paul Anthony Gilkerson

IPC: G06F9/30 ,  G06F11/34

Abstract: A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit 4 processes at least one selected instruction, then the trace circuit generates a trace data element including a traced condition value indicating at least the subset of condition flags required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

公开(公告)号：US09378113B2

公开(公告)日：2016-06-28

申请号：US14104382

申请日：2013-12-12

Applicant: ARM Limited

Inventor： Paul Anthony Gilkerson ,  John Michael Horley ,  Michael John Gibbs

IPC: G06F11/00 ,  G06F11/34 ,  G06F9/30

CPC classification number: G06F11/3495 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30145 ,  G06F11/348

Abstract: A trace unit, diagnostic apparatus and data processing apparatus are provided for tracing of conditional instructions. The data processing apparatus generates instruction observed indicators indicating execution of conditional instructions and result output indicators indicating output by the data processing apparatus of results of executing respective conditional instructions. The instruction observed indicators and result output indicators are received by a trace unit that is configured to output conditional instruction trace data items and independently output conditional result trace data items enabling separate trace analysis of conditional instructions and corresponding conditional results by a diagnostic apparatus. The instruction observed indicator is received at the trace unit in a first processing cycle of the data processing apparatus while result output indicator is received at in a second different processing cycle.

Abstract translation: 提供跟踪单元，诊断装置和数据处理装置用于跟踪条件指令。 数据处理装置产生指示执行条件指令的指示观察指示，以及指示数据处理装置执行各条件指令的结果的结果输出指示符。 指令观察指标和结果输出指示器被配置为输出条件指令跟踪数据项的跟踪单元接收，并独立地输出条件结果跟踪数据项，从而能够通过诊断设备对条件指令和相应的条件结果进行单独的跟踪分析。 在数据处理装置的第一处理周期中，在跟踪单元处接收指示观察指示符，而在第二不同处理周期接收结果输出指示符。

公开(公告)号：US09348688B2

公开(公告)日：2016-05-24

申请号：US14185121

申请日：2014-02-20

Applicant: ARM LIMITED

Inventor： John Michael Horley ,  Paul Anthony Gilkerson ,  Michael John Gibbs

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/36 ,  G06F11/34

CPC classification number: G06F11/079 ,  G06F11/3024 ,  G06F11/3466 ,  G06F11/348 ,  G06F11/364 ,  G06F11/3664

Abstract: A data processing apparatus is provided with trace circuitry for generating a plurality of trace streams including an instruction trace stream 10 and a data trace stream 12. The instruction elements within the instruction trace stream and the data elements within the data trace stream are marked with key values KV such that a match may be made between data elements and corresponding instruction elements. When predetermined conditions are met, synchronization markers 66 are inserted in both the instruction trace stream 10 and the data trace stream 12 in order to permit a precise correlation to be made between the instruction elements and the data elements when the data is subsequently analyzed.

Abstract translation: 数据处理装置具有跟踪电路，用于产生包括指令跟踪流10和数据跟踪流12的多个跟踪流。指令跟踪流内的指令元素和数据跟踪流内的数据元素用键标记 值KV，使得可以在数据元素和对应的指令元素之间进行匹配。 当满足预定条件时，同步标记66插入指令跟踪流10和数据跟踪流12两者中，以便在随后分析数据时允许在指令元素和数据元素之间进行精确的相关。

公开(公告)号：US09229908B2

公开(公告)日：2016-01-05

申请号：US13934741

申请日：2013-07-03

Applicant: ARM Limited

Inventor： John Michael Horley ,  Andrew Brookfield Swaine ,  Michael John Williams

IPC: G06F17/10 ,  G06F7/02 ,  G06F7/76

CPC classification number: G06F17/10 ,  G06F7/02 ,  G06F7/76 ,  G06F7/764

Abstract: A data processing apparatus is provided which is configured to select 2M selected identifiers within a possible range of up to 2N identifiers, where M≦N. The data processing apparatus comprises a selection storage unit configured to store at least N+1 identifier selection bits, wherein a position of a first marker bit in the at least N+1 identifier selection bits determines M, and an identifier selection unit configured to determine the 2M selected identifiers. The 2M selected identifiers fall within a range defined by a base identifier and a ceiling identifier. N-M bits of the N+1 identifier selection bits form N-M bits of the base identifier, and M zeroes form a further M bits of the base identifier. The ceiling identifier corresponds to the base identifier, except that the M zeroes of the base identifier are replaced by M ones.

Abstract translation: 提供了一种数据处理装置，其被配置为在最多2N个标识符的可能范围内选择2M个选择的标识符，其中M＆N; E; N。 数据处理装置包括：选择存储单元，被配置为存储至少N + 1个标识符选择位，其中，所述至少N + 1个标识符选择位中的第一标记位的位置确定M;以及标识符选择单元， 2M选择的标识符。 2M个选择的标识符落在由基本标识符和上限标识符定义的范围内。 N + 1标识符选择位的N-M位形成基本标识符的N-M位，并且M个零构成基本标识符的另外M位。 天花板标识符对应于基本标识符，除了基本标识符的M个零被M 1替换。