公开(公告)号：US20240264838A1

公开(公告)日：2024-08-08

申请号：US18106560

申请日：2023-02-07

Applicant: Arm Limited

Inventor： Mbou EYOLE

IPC: G06F9/38 ,  G06F9/50 ,  G06N20/00

CPC classification number: G06F9/3806 ,  G06F9/5044 ,  G06N20/00

Abstract: Prediction circuitry for a data processing system comprises input circuitry to receive status inputs associated with instructions or memory access requests processed by the data processing system. Unified predictor circuitry comprises shared hardware circuitry configurable to act as a plurality of different types of predictor. The unified predictor circuitry generates, according to a unified prediction algorithm based on the status inputs and a set of predictor parameters, an array of predictions comprising different types of prediction of instruction/memory-access behaviour for the data processing system. A configuration subset of the predictor parameters is configurable to adjust a relative influence of each status input in the unified prediction algorithm used to generate the array of predictions. Output circuitry outputs, based on the plurality of types of prediction, speculative action control signals for controlling the data processing system to perform speculative actions.

公开(公告)号：US20240086202A1

公开(公告)日：2024-03-14

申请号：US17942554

申请日：2022-09-12

Applicant: Arm Limited

Inventor： Matthew James WALKER ,  Mbou EYOLE ,  Giacomo GABRIELLI ,  Balaji VENU ,  Wei WANG

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/32

CPC classification number: G06F9/3855 ,  G06F9/30145 ,  G06F9/32

Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

公开(公告)号：US20180210733A1

公开(公告)日：2018-07-26

申请号：US15745478

申请日：2016-06-15

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Jacob EAPEN ,  Mbou EYOLE

IPC: G06F9/30

CPC classification number: G06F9/30192 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043

Abstract: An apparatus and a method are provided for performing a splice operation, the apparatus having a set of vector registers and one or more control registers. Processing circuitry is arranged to execute a sequence of instructions including a splice instruction that identifies at least a first vector register and at least one control register. The first vector register stores a first vector of data elements having a vector length, and the at least one control register stores control data identifying one or more data elements occupying sequential data element positions within the first vector of data elements. The processing circuitry is responsive to execution of the splice instruction to extract from the first vector each data element identified by the control data in the at least one control register, and to output the extracted data elements within sequential data element positions of the result vector starting from a first end of the result vector, and data elements from a second vector are output to the remaining result vector data element positions not occupied by the extracted data elements from the first vector.

公开(公告)号：US20180210731A1

公开(公告)日：2018-07-26

申请号：US15743735

申请日：2016-07-28

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Mbou EYOLE ,  Alejandro MARTINEZ VICENTE

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30072 ,  G06F9/30076 ,  G06F9/325

Abstract: Data processing apparatus comprises processing circuitry to selectively apply a vector processing operation to data items at positions within data vectors according to the states of a set of respective predicate flags associated with the positions, the data vectors having a data vector processing order, each data vector comprising a plurality of data items having a data item order, the processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry; wherein the instruction decoder circuitry is responsive to a propagation instruction to control the instruction processing circuitry to derive a set of predicate flags applicable to a current data vector in dependence upon a set of predicate flags applicable to a preceding data vector in the data vector processing order, wherein when one or more last-most predicate flags of the set applicable to the preceding data vector are inactive, all of the derived predicate flags in the set applicable to the current data vector are inactive.

公开(公告)号：US20170168820A1

公开(公告)日：2017-06-15

申请号：US15371670

申请日：2016-12-07

Applicant: ARM Limited

Inventor： Mbou EYOLE ,  Matthias Lothar BOETTCHER

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30076 ,  G06F9/3016 ,  G06F9/30189 ,  G06F9/3814 ,  G06F9/3887

Abstract: Data processing apparatus comprises vector processing circuitry to apply a vector processing instruction to data vectors having a data vector length, each data vector comprising a plurality of data items equal in number to the data vector length, the vector processing circuitry having circuitry defining a plurality of processing lanes, there being at least as many processing lanes as a maximum data vector length; and control circuitry to selectively vary the data vector length used by the vector processing circuitry amongst a plurality of possible data vector length values up to the maximum data vector length and to disable operation of a subset of the processing lanes so that the disabled subset of processing lanes are unavailable for use by the vector processing circuitry and there remain at least as many enabled processing lanes as the data vector length set by the control circuitry.

公开(公告)号：US20230120783A1

公开(公告)日：2023-04-20

申请号：US17905225

申请日：2020-12-21

Applicant: ARM LIMITED

Inventor： Mbou EYOLE ,  Michiel Willem VAN TOL ,  Stefanos KAXIRAS

IPC: G06F9/38

Abstract: Apparatuses and methods are provided, relating to the control of data processing in devices which comprise both decoupled access-execute processing circuitry and prefetch circuitry. Control of the access portion of the decoupled access-execute processing circuitry may be dependent on a performance metric of the prefetch circuitry. Alternatively or in addition, control of the prefetch circuitry may be dependent on a performance metric of the access portion.

公开(公告)号：US20210349721A1

公开(公告)日：2021-11-11

申请号：US17211062

申请日：2021-03-24

Applicant: Arm Limited

Inventor： Mbou EYOLE ,  Michiel Willem VAN TOL

IPC: G06F9/30 ,  G06F9/38

Abstract: Apparatuses and methods for handling load requests are disclosed. In response to a load request specifying a data item to retrieve from memory, a series of data items comprising the data item identified by the load request are retrieved. Load requests are buffered prior to the load requests being carried out. Coalescing circuitry determines for the load request and a set of one or more other load requests buffered in the pending load buffer circuitry whether an address proximity condition is true. The address proximity condition is true when all data items identified by the set of one or more other load requests are comprised within the series of data items. When the address proximity condition is true, the set of one or more other load requests are suppressed. Coalescing prediction circuitry generate a coalescing prediction for each load request based on previous handling of load requests by the coalescing circuitry.

公开(公告)号：US20210342156A1

公开(公告)日：2021-11-04

申请号：US17215394

申请日：2021-03-29

Applicant: Arm Limited

Inventor： Mbou EYOLE ,  Michiel Willem VAN TOL

IPC: G06F9/38 ,  G06F9/30

Abstract: Apparatuses and methods for instruction scheduling in an out-of-order decoupled access-execute processor are disclosed. The instructions for the decoupled access-execute processor comprises access instructions and execute instructions, where access instructions comprise load instructions and instructions which provide operand values to load instructions. Schedule patterns of groups of linked execute instructions are monitored, where the execute instructions in a group of linked execute instructions are linked by data dependencies. On the basis of an identified repeating schedule pattern configurable execution circuitry adopts a configuration to perform the operations defined by the group of linked execute instructions of the repeating schedule pattern.

公开(公告)号：US20210117200A1

公开(公告)日：2021-04-22

申请号：US16658494

申请日：2019-10-21

Applicant: Arm Limited

Inventor： Mbou EYOLE

IPC: G06F9/38 ,  G06F12/0875

Abstract: Data processing apparatuses, methods of data processing, instructions, and simulator computer programs for providing a corresponding instruction execution environment are disclosed. Decode circuitry is responsive to an instance of a predetermined instruction type to cause issue circuitry to issue at least one subsequent instruction for execution to one of first and second instruction execution circuitry which support decoupled access-execute instruction execution. The predetermined instruction type is thus a steering instruction for at least one subsequent instruction and the programmer is provided with a mechanism for determining which program instructions are treated as access instructions and which are treated as execute instructions.

公开(公告)号：US20210026628A1

公开(公告)日：2021-01-28

申请号：US16630614

申请日：2018-07-02

Applicant: ARM LIMITED

Inventor： Eric BISCONDI ,  Mbou EYOLE

IPC: G06F9/30

Abstract: Apparatuses, methods, programs, and complex number processing instructions are provided to support vector processing operations on input data vectors comprising a plurality of input data items at respective positions in the input data vectors. In response to the instructions at least one first set of data items is extracted from alternating positions in a first source register and at least one second set of data items is extracted from alternating positions in the second source register, wherein consecutive data items in the first and second source registers comprise alternating real and imaginary components of respective sets of complex numbers. A result set of complex number components is generated using the two sets of data items as operands, and the result set of complex number components is one of a real part and an imaginary part of a complex number result of the complex number operation applied to the two sets of complex numbers. The result set of complex number components is applied to the destination register.