公开(公告)号：US20170351517A1

公开(公告)日：2017-12-07

申请号：US15538365

申请日：2015-11-23

Applicant: ARM LIMITED

Inventor： Stephan DIESTELHORST ,  Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE ,  Matthew James HORSNELL

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08 ,  G06F12/126

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/455 ,  G06F9/46 ,  G06F9/467 ,  G06F11/362 ,  G06F11/3636 ,  G06F12/08 ,  G06F12/126

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated. The non-standard response signal may be used to initiate the request source to follow a subsequent path of processing different from that which it would otherwise follow. Support is also provided for detecting a trigger condition which results in the halting (freezing) of a partially completed transaction and the saving the speculative updates associated with that partially completed transaction to the architectural state of the system.

公开(公告)号：US20160292021A1

公开(公告)日：2016-10-06

申请号：US15066453

申请日：2016-03-10

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  Simon John CRASKE

IPC: G06F9/54 ,  G06F9/52

CPC classification number: G06F9/542

Abstract: In an apparatus performing multi-threaded data processing event handling circuitry receives event information from the data processing circuitry indicative of an event which has occurred during the data processing operations. Visibility configuration storage holds a set of visibility configuration values, each visibility configuration value associated with a thread of the multiple threads and the event handling circuitry adapts its use of the event information to restrict visibility of the event information for software of threads other than the thread which generated the event information when a visibility configuration value for the thread which generated the event information has a predetermined value. This allows multi-threaded event monitoring to be supported, whilst protecting event information from a particular thread for which it is desired to limit its visibility to software of other threads.

Abstract translation: 在执行多线程数据处理的装置中，事件处理电路从表示在数据处理操作期间发生的事件的数据处理电路接收事件信息。 可见性配置存储保存一组可见性配置值，与多个线程的线程相关联的每个可见性配置值和事件处理电路适应其对事件信息的使用，以限制线程以外的线程的事件信息的可见性 当生成事件信息的线程的可见性配置值具有预定值时，生成事件信息。 这允许支持多线程事件监视，同时保护来自希望限制其对其他线程的软件的可见性的特定线程的事件信息。

公开(公告)号：US20160239403A1

公开(公告)日：2016-08-18

申请号：US15007578

申请日：2016-01-27

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS

IPC: G06F11/36

CPC classification number: G06F11/3636 ,  G06F11/3644

Abstract: An apparatus and method are provided for controlling debugging of program instructions that include a transaction, where the transaction is executed on processing circuitry and comprises a number of program instructions that execute to generate updates to state data, and where those updates are only committed if the transaction completes without a conflict. In addition to the processing circuitry, the apparatus has control storage for storing at least one watchpoint identifier, and the processing circuitry is then arranged, when detecting a watchpoint match condition with reference to the at least one watchpoint identifier during execution of a program instruction within the transaction, to create a pending watchpoint debug event. The processing circuitry is then responsive to execution of the transaction finishing to initiate a watchpoint debug event for the pending watchpoint debug event. However, if instead the transaction is aborted before it finishes (due to a conflict arising), the processing circuitry is arranged to cancel the pending watchpoint debug event. Such an approach prevents a probe effect arising during execution of a transaction due to debugging activity.

Abstract translation: 提供了一种用于控制包括交易的程序指令的调试的装置和方法，其中交易在处理电路上执行，并且包括执行以生成对状态数据的更新的多个程序指令，以及仅在 事务完成没有冲突。 除了处理电路之外，该装置具有用于存储至少一个观察点标识符的控制存储器，并且随后在执行程序指令期间参考至少一个观察点标识符检测观察点匹配条件时，处理电路被布置 该事务，以创建一个挂起的观察点调试事件。 处理电路然后响应于事务处理的执行以启动用于挂起的观察点调试事件的观察点调试事件。 但是，如果交易在完成之前中止（由于产生冲突），则处理电路被安排为取消挂起的观察点调试事件。 这种方法防止由于调试活动而在执行交易期间产生的探针效应。

公开(公告)号：US20230214224A1

公开(公告)日：2023-07-06

申请号：US17998299

申请日：2021-05-13

Applicant: Arm Limited

Inventor： John Michael HORLEY ,  Michael John WILLIAMS ,  Mark Salling RUTLAND ,  Alasdair GRANT

IPC: G06F9/38

CPC classification number: G06F9/3865 ,  G06F9/3867

Abstract: A technique for collecting state information of an apparatus comprising a processing pipeline for executing a sequence of instructions, and interesting instruction designation circuitry for identifying at least one of the instructions in the sequence as being an interesting instruction. Each interesting instruction is an instruction for which given state information of the apparatus associated with execution of that interesting instruction is to be collected. The interesting instruction designation circuitry is arranged, for each identified interesting instruction, to apply defined selection criteria to determine a further instruction later in the sequence of instructions than the interesting instruction, and to mark that further instruction as having a synchronous exception associated therewith. The processing pipeline is responsive to the further instruction, which causes the processing pipeline to execute a given exception handling routine in order to collect the given state information.

公开(公告)号：US20190163601A1

公开(公告)日：2019-05-30

申请号：US16321503

申请日：2017-08-10

Applicant: ARM LIMITED

Inventor： François Christopher Jacques BOTMAN ,  Thomas Christopher GROCUTT ,  John Michael HORLEY ,  Michael John WILLIAMS

IPC: G06F11/34 ,  G06F11/36 ,  G06F9/38

Abstract: An apparatus and method are provided to control assertion of a trigger signal to processing circuitry. The apparatus has evaluation circuitry to receive program instruction execution information indicative of a program instruction executed by the processing circuitry, which is arranged to perform an evaluation operation to determine with reference to evaluation information whether the program instruction execution information indicates presence of a trigger condition. Trigger signal generation circuitry is used to assert a trigger signal to the processing circuitry in dependence on whether the trigger condition is determined to be present. Further, filter circuitry is arranged to receive event information indicative of at least one event occurring within the processing circuitry, and is arranged to determine with reference to filter control information and that event information whether a qualifying condition is present. The filter circuitry is arranged, on determining that the qualifying condition is not present, to prevent the presence of the trigger condition being

公开(公告)号：US20180203756A1

公开(公告)日：2018-07-19

申请号：US15743392

申请日：2016-06-21

Applicant: ARM LIMITED

Inventor： Nigel John STEPHENS ,  Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/079 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/3865 ,  G06F11/0721 ,  G06F11/0751 ,  G06F11/0793

Abstract: A data processing system (2) supports non-speculative execution of vector load instructions that perform at least one contingent load of a data value. Fault detection circuitry (26) serves to detect whether a contingent load is fault-generating contingent load or a fault-free contingent load. Contingent load suppression circuitry (28) detects and suppresses a fault-free contingent load that matches a predetermined criteria that may result in an undesired change of architectural state (undesired side-effect). Examples of such predetermined criteria are that the contingent load is to a non-memory device or that the contingent load will trigger a diagnostic response such as entry of a halting debug halting mode or triggering of a debug exception.

公开(公告)号：US20170337115A1

公开(公告)日：2017-11-23

申请号：US15532286

申请日：2015-11-23

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  John Michael HORLEY ,  Stephan DIESTELHORST

IPC: G06F11/36 ,  G06F9/46

CPC classification number: G06F9/30043 ,  G06F9/3004 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/455 ,  G06F9/46 ,  G06F9/467 ,  G06F11/362 ,  G06F11/3636 ,  G06F12/08 ,  G06F12/126

Abstract: A data processing apparatus (4) includes processing circuitry (6) for executing program instructions that form part of a transaction which executes to generate speculative updates and to commit the speculative updates if the transaction completes without a conflict. Instruction sampling circuitry (44) captures instruction diagnostic data (IDD) relating to execution of a sampled instruction. Transaction tracking circuitry (46) detects if the sampled instruction is within a transaction and if so, tracks whether the speculative updates associated with the transaction are committed and captures transaction diagnostic data (TDD) indicative of whether or not the speculative updates were committed. Thus, both instruction diagnostic data relating to a sampled instruction and transaction diagnostic data relating to the fate of a transaction containing a sampled instruction are captured.

公开(公告)号：US20160371501A1

公开(公告)日：2016-12-22

申请号：US15189284

申请日：2016-06-22

Applicant: ARM LIMITED

Inventor： John Michael HORLEY ,  Michael John WILLIAMS ,  Simon John CRASKE ,  Uma Maheswari RAMALINGAM

IPC: G06F21/62

CPC classification number: G06F21/74

Abstract: A data processing apparatus comprises a processing element having associated memory storage and one or more registers, the processing element being configured to perform processing activities in two or more security modes so as to inhibit a processing activity performed in one of the security modes from accessing at least some information associated with a processing activity performed in another of the security modes; in which the processing element is configured, in response to a function call causing a branch from a processing activity in a first security mode to a processing activity in a second security mode, to store the contents of one or more of the registers in the memory storage and, in response to a branch return to the first security mode, to retrieve the register contents from the memory storage; and trace apparatus configured to generate items of trace data indicative of processing activities of the processing element; in which the trace apparatus is configured to detect a branch return operation by the processing element and to generate one or more items of trace data relating to the branch return operation; and in which the trace apparatus is configured to detect the processing element retrieving register contents from the memory storage in response to a branch return to the first security mode and to generate one or more further items of trace data relating to the retrieval of the register contents from the memory storage.

Abstract translation: 数据处理装置包括具有相关联的存储器存储器和一个或多个寄存器的处理元件，处理元件被配置为以两个或更多个安全模式执行处理活动，以便禁止在一个安全模式中执行的处理活动以访问 至少一些与另一个安全模式中执行的处理活动相关联的信息; 其中处理元件被配置为响应于使分支从第一安全模式中的处理活动转移到第二安全模式中的处理活动的功能调用，以将一个或多个寄存器的内容存储在存储器中 并且响应于分支返回到第一安全模式，从存储器存储器检索寄存器内容; 以及跟踪装置，被配置为生成指示所述处理元件的处理活动的跟踪数据项; 其中所述跟踪装置被配置为检测所述处理元件的分支返回操作并且生成与所述分支返回操作有关的一个或多个跟踪数据项; 并且其中所述跟踪装置被配置为响应于到所述第一安全模式的分支返回而检测所述处理元件从所述存储器存储器检索寄存器内容，并且生成与所述寄存器内容的检索相关的跟踪数据的一个或多个其它项目 从内存存储。

公开(公告)号：US20160239404A1

公开(公告)日：2016-08-18

申请号：US15007604

申请日：2016-01-27

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS

IPC: G06F11/36

CPC classification number: G06F11/3644 ,  G06F11/3636

Abstract: An apparatus and method are provided for controlling debugging of program instructions executed on processing circuitry, where the program instructions include a transaction comprising a number of program instructions that execute to generate updates to state data, with the processing circuitry then committing the updates if the transaction completes without a conflict. In addition to the processing circuitry, the apparatus has control storage for storing stepping control data used to control operation of the processing circuitry. The processing circuitry is responsive to the stepping control data having a first value to operate in a single stepping mode, where the processing circuitry initiates a debug event following execution of each instruction. However, if the stepping control data has a second value, the processing circuitry instead is arranged to operate in a step over transaction mode, where the processing circuitry is arranged, when executing the number of program instructions within the transaction, to suppress initiation of the debug event until the transaction has completed. By enabling the processing circuitry to operate in the step over transaction mode, this can avoid probe effects being introduced by debug activity during the execution of the program instructions of a transaction.

Abstract translation: 提供了一种用于控制在处理电路上执行的程序指令的调试的装置和方法，其中程序指令包括包括执行以产生对状态数据的更新的多个程序指令的事务，其中处理电路然后在进行交易时提交更新 完成没有冲突。 除了处理电路之外，该装置具有用于存储用于控制处理电路的操作的步进控制数据的控制存储器。 处理电路响应于具有第一值的步进控制数据以单步进模式操作，其中处理电路在执行每个指令之后启动调试事件。 然而，如果步进控制数据具有第二值，则处理电路被设置为在执行处理电路的事务模式的步骤中操作，当在事务中执行程序指令的数量时，抑制 调试事件，直到事务完成。 通过使处理电路能够在事务模式的步骤中操作，这可以避免在执行事务的程序指令期间由调试活动引入的探测效应。

公开(公告)号：US20140344621A1

公开(公告)日：2014-11-20

申请号：US14448038

申请日：2014-07-31

Applicant: ARM Limited

Inventor： Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE

IPC: G06F11/22

CPC classification number: G06F11/2236 ,  G06F11/3632

Abstract: A method and apparatus for controlling a processor to execute in a single step mode such that a single instruction from the instruction stream is executed, the processor determines if the single instruction is one of at least one predetermined type of instruction and stores a type indicator in a data storage location and a diagnostic exception is taken after the processor has processed the single instruction. Additionally, a diagnostic operation is performed including accessing the type indicator stored in the data storage location and, when the single instruction was not one of the predetermined type, controlling the processor to continue executing instructions in the single step mode, and, when the single instruction was one of the at least one predetermined type, controlling the processor to exit the single step mode and not execute the next instruction within the instruction stream as a single instruction followed by an exception.

Abstract translation: 一种用于控制处理器以单步模式执行使得来自指令流的单个指令被执行的方法和装置，处理器确定单个指令是否是至少一种预定类型的指令中的一种，并将类型指示器存储在 在处理器处理单个指令之后，采集数据存储位置和诊断异常。 此外，执行诊断操作，包括访问存储在数据存储位置中的类型指示符，并且当单个指令不是预定类型中的一个时，控制处理器以单步模式继续执行指令，并且当单个指令 指令是至少一种预定类型之一，控制处理器退出单步模式，并且不执行指令流内的下一条指令作为跟随异常的单个指令。