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公开(公告)号：US20160246543A1
公开(公告)日：2016-08-25
申请号：US15008569
申请日：2016-01-28
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS , John Michael HORLEY
IPC: G06F3/06
CPC classification number: G06F11/3636
Abstract: An apparatus for generating a trace stream, a method for generating a trace stream, an apparatus for receiving a trace stream and a method of receiving a trace stream are provided. Header items and payload items in the trace stream are respectively grouped together into a contiguous sequence of header items and a contiguous sequence of payload items. This can for example facilitate the production of a trace stream in which the trace stream is aligned to a predetermined length (e.g. corresponding to an alignment of a memory in which the trace stream is to be stored) thus facilitating its interpretation.
Abstract translation: 提供了一种用于生成跟踪流的装置，用于产生跟踪流的方法，用于接收跟踪流的装置和接收跟踪流的方法。 跟踪流中的报头项目和有效负载项目分别分组在一起，连续的报头项目序列和有效载荷项目的连续序列。 这可以例如促进跟踪流的生成，其中跟踪流被对准到预定长度（例如，对应于其中要存储跟踪流的存储器的对准），因此有助于其解释。
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公开(公告)号：US20160154654A1
公开(公告)日：2016-06-02
申请号：US14952807
申请日：2015-11-25
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS , Richard Roy GRISENTHWAITE , Simon John CRASKE
CPC classification number: G06F9/3861 , G06F9/522 , G06F11/0721 , G06F11/0793
Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.
Abstract translation: 提供了数据处理装置和数据处理方法。 响应于数据处理指令执行数据处理操作。 如果数据处理操作未成功，则设置错误异常条件。 确定是否存在错误存储器障碍条件，并且根据是否存在错误存储器屏障条件来执行错误存储器屏障过程。 错误存储器屏障过程包括：如果设置了错误异常条件，并且设置了错误掩码条件：设置延迟错误异常条件并清除错误异常条件。
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3.发明申请公开(公告)号：US20160048440A1
公开(公告)日：2016-02-18
申请号：US14747141
申请日：2015-06-23
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS , Simon John CRASKE
CPC classification number: G06F11/348 , G06F11/1484 , G06F11/301 , G06F11/3024 , G06F11/3409 , G06F11/3433 , G06F11/3466 , G06F2201/815 , G06F2201/86 , G06F2201/88
Abstract: A data processing apparatus has processing circuitry which can execute instructions at one of several privilege levels. A plurality of performance monitoring circuits are included. In response to an instruction executed at a first privilege level, first configuration data can be set for controlling performance monitoring by a first subset of performance monitoring circuits. A disable control flag can be set in response to an instruction executed at a second privilege level higher than the first privilege level. If the disable control flag has a predetermined value then performance monitoring control circuitry disables performance monitoring by the first subset of performance monitoring circuits while the processing circuitry is executing instructions at the second privilege level.
Abstract translation: 数据处理装置具有能够以几个特权级别中的一个执行指令的处理电路。 包括多个性能监视电路。 响应于在第一特权级执行的指令，可以设置第一配置数据以控制性能监视电路的第一子集的性能监视。 可以响应于在高于第一特权级别的第二特权级别执行的指令来设置禁用控制标志。 如果禁用控制标志具有预定值，则性能监视控制电路在处理电路正在执行第二特权级别的指令时，禁用性能监视电路的第一子集的性能监视。
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公开(公告)号：US20210034362A1
公开(公告)日：2021-02-04
申请号：US16975486
申请日：2019-02-15
Applicant: Arm Limited
Inventor： Michael John WILLIAMS , Nigel John STEPHENS
IPC: G06F9/30
Abstract: Data processing apparatus comprises vector processing circuitry to selectively apply vector processing operations defined by vector processing instructions to generate one or more data elements of a data vector comprising a plurality of data elements at respective data element positions of the data vector, according to the state of respective predicate flags associated with the positions of the data vector; and generator circuitry to generate instruction sample data indicative of processing activities of the vector processing circuitry for selected ones of the vector processing instructions, instruction sample data indicating at least the state of the predicate flags at execution of the selected vector processing instructions.
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公开(公告)号：US20180260227A1
公开(公告)日：2018-09-13
申请号：US15555239
申请日：2016-02-11
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS , John Michael HORLEY , Stephan DIESTELHORST , Richard Roy GRISENTHWAITE
Abstract: There is provided an apparatus comprising processing circuitry to execute a transaction comprising a number of program instructions that execute to generate updates to state data, to commit the updates if the transaction completes without a conflict, and to generate trace control signals during execution of the number of program instructions. The processing circuitry uses at least one resource during execution of the program instructions. Transaction trace circuitry generates trace items in response to the trace control signals. In response to the trace control signals indicating that a change in a usage level of the at least one resource has occurred during execution of the program instructions, the transaction trace circuitry generates at least one trace item that indicates the usage level of the at least one resource.
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Patent Agency Ranking
公开(公告)号：US20170212844A1
公开(公告)日：2017-07-27
申请号：US15002648
申请日：2016-01-21
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS , Michael FILIPPO , Hazim SHAFI
CPC classification number: G06F12/1027 , G06F3/0611 , G06F3/0653 , G06F3/0673 , G06F11/3409 , G06F11/3466 , G06F12/1009 , G06F2212/1024 , G06F2212/68
Abstract: An apparatus includes processing circuitry to process instructions, some of which may require addresses to be translated. The apparatus also includes address translation circuitry to translate addresses in response to instruction processed by the processing circuitry. Furthermore, the apparatus also includes translation latency measuring circuitry to measure a latency of at least part of an address translation process performed by the address translation circuitry in response to a given instruction.
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公开(公告)号：US20160239405A1
公开(公告)日：2016-08-18
申请号：US15140514
申请日：2016-04-28
Applicant: ARM Limited
Inventor： Michael John WILLIAMS , Richard Roy GRISENTHWAITE , Simon John CRASKE
CPC classification number: G06F11/3644 , G06F9/3004 , G06F9/30112 , G06F9/30149 , G06F9/30189 , G06F9/45554 , G06F11/3648
Abstract: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.
Abstract translation: 提供了包括数据处理电路和调试电路的数据处理装置。 当在调试模式下操作时，调试电路控制处理电路的操作。 数据处理电路在进入调试模式时确定数据处理装置的当前操作状态。 数据处理电路根据确定的当前操作状态分配要用作调试指令集的多个指令集中的一个。
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公开(公告)号：US20230385196A1
公开(公告)日：2023-11-30
申请号：US18320407
申请日：2023-05-19
Applicant: Arm Limited
Inventor： Michael John WILLIAMS , John Michael HORLEY
IPC: G06F12/0815
CPC classification number: G06F12/0815
Abstract: Data processing apparatuses and methods of data processing are disclosed wherein a processing element maintains a buffer in the memory in support of the data processing it performs. A write pointer indicates a current write location in the buffer. A cache holds copies of the data which are subject to the data processing operations and allocations into the cache from the memory and write-backs from the cache to the memory are performed in cache line units of data. When the processing element performs a data write to the buffer at a location determined by the write pointer, the processor updates the write pointer in an update direction corresponding to a progression direction of data writes in the buffer, and further locations in the progression direction in the buffer between the location indicated by the write pointer and a boundary location are signalled to be written with a predetermined value.
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公开(公告)号：US20230289279A1
公开(公告)日：2023-09-14
申请号：US18007233
申请日：2021-08-02
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS
IPC: G06F11/34
CPC classification number: G06F11/348 , G06F2201/88 , G06F2201/86 , G06F2201/81
Abstract: A data processing apparatus and method having processing circuitry, and trace circuitry having a trace buffer; write pointer storage, and a call depth counter, wherein the trace circuitry generates trace data processing first event activities: modify the call depth counter in a first direction, store first trace data indicative of the first event, and modify the write pointer to point to a next location in the trace buffer; in response to a second event, when the call depth counter is not equal to a threshold call depth, to: modify the call depth counter direction and the write pointer to point to a previous location in the trace buffer; and in response to the second event, when the call depth counter is equal to the threshold call depth, to store second trace data indicative of the second event in the trace buffer at the current location.
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公开(公告)号：US20190340097A1
公开(公告)日：2019-11-07
申请号：US16305184
申请日：2017-05-15
Applicant: ARM LIMITED
Inventor： Michael John WILLIAMS
Abstract: Statistical sampling of diagnostic data within an apparatus for processing data 2 is performed based upon sample interval monitoring and address monitoring. A program instruction has its diagnostic data stored when it meets a sample interval criteria and an address match criteria. The address match may correspond to an instruction address of the program instruction or a target address to be read or written by the program instruction.
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