公开(公告)号：US20180373898A1

公开(公告)日：2018-12-27

申请号：US15739825

申请日：2016-05-26

Applicant: ARM Limited

Inventor： Thomas Christopher GROCUTT ,  Simon John CRASKE

IPC: G06F21/74 ,  G06F21/52 ,  G06F12/14 ,  G06F9/445

Abstract: A data processing apparatus is provided which uses flag circuitry (174) to set an access tracking flag (SFPA) to a first value when the processing circuitry (154) enters a secure mode in association with a function call and to switch the access tracking flag to a second value upon detection of a first access of at least one type to predetermined state data, such as floating point register data, by processing circuitry operating in the secure mode in association with that function call. This access tracking flag may then be used in association with a lazy-protection program instruction (VLSTM) and a lazy-load program instruction (VLLDM) to control whether or not push operations of the state data and restore operations of the state data are performed in order to prevent access in the non-secure mode to that state data.

公开(公告)号：US20160357565A1

公开(公告)日：2016-12-08

申请号：US15133329

申请日：2016-04-20

Applicant: ARM LIMITED

Inventor： Peter Richard GREENHALGH ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/38 ,  G06F1/32 ,  G06F9/30

Abstract: Apparatus for processing data 2 is provided with fetch circuitry 16 for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry 22, 24 has a first operating mode and a second operating mode. Mode switching circuitry 30 switches the pipeline circuitry 22, 24, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline 22 to perform interleaved multiple thread processing. The second operating mode may utilise an out-of-order processing pipeline 24 for performing out-of-order processing.

Abstract translation: 用于处理数据2的装置具有取出电路16，用于从具有相应程序计数器值的指令的一个或多个有效线程获取用于执行的程序指令。 管道电路22,24具有第一操作模式和第二操作模式。 模式切换电路30根据具有可执行程序指令的程序指令的有效线程数，在第一操作模式和第二操作模式之间切换流水线电路22,24。 第一操作模式具有比第二操作模式执行的每个指令更低的平均能量消耗，并且第二操作模式对于单线程具有比第一操作模式更高的平均指令执行速率。 第一操作模式可以利用桶处理流水线22执行交错多线程处理。 第二操作模式可以利用无序处理流水线24来执行无序处理。

公开(公告)号：US20160154654A1

公开(公告)日：2016-06-02

申请号：US14952807

申请日：2015-11-25

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  Richard Roy GRISENTHWAITE ,  Simon John CRASKE

IPC: G06F9/38 ,  G06F9/52

CPC classification number: G06F9/3861 ,  G06F9/522 ,  G06F11/0721 ,  G06F11/0793

Abstract: Apparatus for data processing and a method of data processing are provided. Data processing operations are performed in response to data processing instructions. An error exception condition is set if a data processing operation has not been successful. It is determined if an error memory barrier condition exists and an error memory barrier procedure is performed in dependence on whether the error memory barrier condition exists. The error memory barrier procedure comprises, if the error exception condition is set and if an error mask condition is set: setting a deferred error exception condition and clearing the error exception condition.

Abstract translation: 提供了数据处理装置和数据处理方法。 响应于数据处理指令执行数据处理操作。 如果数据处理操作未成功，则设置错误异常条件。 确定是否存在错误存储器障碍条件，并且根据是否存在错误存储器屏障条件来执行错误存储器屏障过程。 错误存储器屏障过程包括：如果设置了错误异常条件，并且设置了错误掩码条件：设置延迟错误异常条件并清除错误异常条件。

公开(公告)号：US20160048440A1

公开(公告)日：2016-02-18

申请号：US14747141

申请日：2015-06-23

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  Simon John CRASKE

IPC: G06F11/34 ,  G06F11/30 ,  G06F11/14

CPC classification number: G06F11/348 ,  G06F11/1484 ,  G06F11/301 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3433 ,  G06F11/3466 ,  G06F2201/815 ,  G06F2201/86 ,  G06F2201/88

Abstract: A data processing apparatus has processing circuitry which can execute instructions at one of several privilege levels. A plurality of performance monitoring circuits are included. In response to an instruction executed at a first privilege level, first configuration data can be set for controlling performance monitoring by a first subset of performance monitoring circuits. A disable control flag can be set in response to an instruction executed at a second privilege level higher than the first privilege level. If the disable control flag has a predetermined value then performance monitoring control circuitry disables performance monitoring by the first subset of performance monitoring circuits while the processing circuitry is executing instructions at the second privilege level.

Abstract translation: 数据处理装置具有能够以几个特权级别中的一个执行指令的处理电路。 包括多个性能监视电路。 响应于在第一特权级执行的指令，可以设置第一配置数据以控制性能监视电路的第一子集的性能监视。 可以响应于在高于第一特权级别的第二特权级别执行的指令来设置禁用控制标志。 如果禁用控制标志具有预定值，则性能监视控制电路在处理电路正在执行第二特权级别的指令时，禁用性能监视电路的第一子集的性能监视。

公开(公告)号：US20140281433A1

公开(公告)日：2014-09-18

申请号：US13795611

申请日：2013-03-12

Applicant: ARM LIMITED

Inventor： John Michael HORLEY ,  Simon John CRASKE

IPC: G06F11/34

CPC classification number: G06F11/0766 ,  G06F11/0721

Abstract: A data processing apparatus comprises processing circuitry for executing a stream of instructions, and exception handling circuitry for selecting, from one or more exceptions, an exception to be handled by the processing circuitry. The unselected exceptions are referred to as pending exceptions. The data processing apparatus further comprises trace generating circuitry that generates trace data packets in dependence on activity of the processing circuitry. The trace generating circuitry detects pending exceptions and, if an exception is detected to be pending, includes an indication of the pending exception in at least one trace data packet. By tracking when a particular exception is pended, rather than when it is selected for handling by the processing circuitry, it is possible to more precisely determine when the exception occurred, as opposed to when it is finally handled.

Abstract translation: 数据处理装置包括用于执行指令流的处理电路和用于从一个或多个异常中选择要由处理电路处理的异常的异常处理电路。 未选择的异常被称为挂起的异常。 数据处理装置还包括跟踪生成电路，其根据处理电路的活动产生跟踪数据分组。 跟踪产生电路检测待处理的异常，并且如果检测到异常待处理，则在至少一个跟踪数据分组中包括挂起异常的指示。 通过跟踪特定异常何时进行，而不是当它被选择用于由处理电路处理时，可以更准确地确定何时发生异常，而不是最终处理何时。

公开(公告)号：US20210026634A1

公开(公告)日：2021-01-28

申请号：US17067852

申请日：2020-10-12

Applicant: ARM LIMITED

Inventor： Simon John CRASKE

IPC: G06F9/30

Abstract: An apparatus comprises processing circuitry for processing program instructions according to a predetermined architecture defining a number of architectural registers accessible in response to the program instructions. A set of hardware registers is provided in hardware. A storage capacity of the set of hardware registers is insufficient for storing all the data associated with the architectural registers of the pre-determined architecture. Control circuitry is responsive to the program instructions to transfer data between the hardware registers and at least one register-emulating memory location in memory for storing data corresponding to the architectural registers of the architecture.

公开(公告)号：US20200257531A1

公开(公告)日：2020-08-13

申请号：US16864223

申请日：2020-05-01

Applicant: ARM Limited

Inventor： Peter Richard GREENHALGH ,  Simon John CRASKE ,  Ian Michael CAULFIELD ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30 ,  G06F9/38

Abstract: A processing pipeline may have first and second execution circuits having different performance or energy consumption characteristics. Instruction supply circuitry may support different instruction supply schemes with different energy consumption or performance characteristics. This can allow a further trade-off between performance and energy efficiency. Architectural state storage can be shared between the execute units to reduce the overhead of switching between the units. In a parallel execution mode, groups of instructions can be executed on both execute units in parallel.

公开(公告)号：US20190057092A1

公开(公告)日：2019-02-21

申请号：US15678430

申请日：2017-08-16

Applicant: ARM LIMITED

Inventor： Simon John CRASKE

IPC: G06F17/30

Abstract: An apparatus comprises: selection circuitry to select the two most preferred items from a set of items having ranking information indicative of an order of preference for the set of items. The selection circuitry comprises at least one selection node circuit, each selection node circuit to receive as inputs an indication of a first pair of items and a second pair of items among the set of items, and comprises first selection circuitry and second selection circuitry. The first selection circuitry to first selection circuitry to select as a first selected item a most preferred one of: a most preferred ranked item of the first pair, and a least preferred item of the second pair. The second selection circuitry to select as a second selected item a most preferred one of: a least preferred item of the first pair, and a most preferred item of the second pair.

公开(公告)号：US20180373630A1

公开(公告)日：2018-12-27

申请号：US15780726

申请日：2016-09-14

Applicant: ARM LIMITED

Inventor： Antony John PENTON ,  Simon John CRASKE

IPC: G06F12/084 ,  G06F12/0815 ,  G06F11/00

Abstract: An apparatus (2) has first processing circuitry (6) and second processing circuitry (4). The second processing circuitry 4 has at least one hardware mechanism (10), (30) providing a greater level of fault protection or fault detection than is provided for the first processing circuitry (6). Coherency control circuitry (45, 80, 82) controls access to data from at least part of a shared address space by the first and second processing circuitry (6, 4) according to an asymmetric coherency protocol in which a local-only update of data in a local cache (8) of the first processing circuitry (6) is restricted in comparison to a local-only update of data in a local cache (8) of the second processing circuitry (4).

公开(公告)号：US20180157490A1

公开(公告)日：2018-06-07

申请号：US15572678

申请日：2016-04-07

Applicant: ARM LIMITED

Inventor： Simon John CRASKE

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/34 ,  G06F11/30 ,  G06F1/32

CPC classification number: G06F9/30149 ,  G06F1/3296 ,  G06F9/3001 ,  G06F9/30076 ,  G06F9/30112 ,  G06F9/30189 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F11/3024 ,  G06F11/3409 ,  G06F11/3466

Abstract: A data processing apparatus (2) operates in a first mode of operation having a first set of processing circuitry (8, 12, 18, 20, 22) ready to perform processing operations and in a second mode of operation having a second set of processing circuitry (8, 12, 14, 18, 20, 22, 24) ready to perform processing operations. A first proper subset (32) of program instructions within the instruction set supported are processed by the processor using a selectable one of the first mode and the second mode. A second proper subset (34) of program instructions within the instruction set are required to be processed by the processor operating in the second mode. Processing circuitry (14, 24) which is inactive in a mode of operation may be placed into a low power state.