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    FLUSHING CONTROL WITHIN A MULTI-THREADED PROCESSOR
    1.
    发明申请
    FLUSHING CONTROL WITHIN A MULTI-THREADED PROCESSOR 审中-公开
    在多螺纹加工器中的冲洗控制

    公开(公告)号：US20160357669A1

    公开(公告)日：2016-12-08

    申请号：US15152775

    申请日：2016-05-12

    Applicant: ARM LIMITED

    Inventor： Peter Richard GREENHALGH

    IPC: G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0804 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/46 ,  G06F12/0811 ,  G06F12/0875 ,  G06F2212/1021 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62

    Abstract: A data processing apparatus 2 performs multi-threaded processing using the processing pipeline 6, 8, 10, 12, 14, 16, 18. Flush control circuitry 30 is responsive to multiple different types of flush trigger. Different types of flush trigger result in different sets of state being flushed for the thread which resulted in the flush trigger with state for other thread not being flushed. For example, a relatively low latency stall may result in flushing back to a first flush point whereas a longer latency stall results in flushing back to a second flush point and the loss of more state data. The data flushed back to the first flushed point may be a subset of the data flushed back to the second flush point.

    Abstract translation: 数据处理装置2使用处理流水线6,8,10,12,14,16,18进行多线程处理。冲洗控制电路30响应于多种不同类型的冲水扳机。 不同类型的刷新触发器导致针对线程刷新的不同状态集合，导致刷新触发器，其他线程未被刷新的状态。 例如，相对较低的延迟停顿可能导致冲洗回到第一个冲洗点，而较长的等待时间延迟会导致冲洗回到第二个冲洗点并丢失更多的状态数据。 刷新回第一冲洗点的数据可以是冲洗回第二冲洗点的数据的子集。

    AN APPARATUS AND METHOD FOR PREDICTING SOURCE OPERAND VALUES AND OPTIMIZED PROCESSING OF INSTRUCTIONS
    2.
    发明申请
    AN APPARATUS AND METHOD FOR PREDICTING SOURCE OPERAND VALUES AND OPTIMIZED PROCESSING OF INSTRUCTIONS 有权

    公开(公告)号：US20210311742A1

    公开(公告)日：2021-10-07

    申请号：US17266759

    申请日：2019-07-17

    Applicant: Arm Limited

    Inventor： Peter Richard GREENHALGH ,  Frederic Claude Marie PIRY ,  Ian Michael CAULFIELD ,  Albin Pierrick TONNERRE

    IPC: G06F9/38 ,  G06F9/30

    Abstract: An apparatus and method are provided for processing instructions. The apparatus has execution circuitry for executing instructions, where each instruction requires an associated operation to be performed using one or more source operand values in order to produce a result value. Issue circuitry is used to maintain a record of pending instructions awaiting execution by the execution circuitry, and prediction circuitry is used to produce a predicted source operand value for a chosen pending instruction. Optimisation circuitry is then arranged to detect an optimisation condition for the chosen pending instruction when the predicted source operand value is such that, having regard to the associated operation for the chosen pending instruction, the result value is known without performing the associated operation. In response to detection of the optimisation condition, an optimisation operation is implemented instead of causing the execution circuitry to perform the associated operation in order to execute the chosen pending instruction. This can lead to significant performance and/or power consumption improvements.

    IMPROVING THE RESPONSIVENESS OF AN APPARATUS TO CERTAIN INTERRUPTS
    4.
    发明申请
    IMPROVING THE RESPONSIVENESS OF AN APPARATUS TO CERTAIN INTERRUPTS 有权

    公开(公告)号：US20210294642A1

    公开(公告)日：2021-09-23

    申请号：US16821151

    申请日：2020-03-17

    Applicant: Arm Limited

    Inventor： Peter Richard GREENHALGH ,  Antony John PENTON

    IPC: G06F9/48 ,  G06F9/38 ,  G06F9/32 ,  G06F9/46 ,  G06F9/54

    Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.

    DATA PROCESSING APPARATUS AND METHOD FOR HANDLING RETRIEVAL OF INSTRUCTIONS FROM AN INSTRUCTION CACHE
    8.
    发明申请
    DATA PROCESSING APPARATUS AND METHOD FOR HANDLING RETRIEVAL OF INSTRUCTIONS FROM AN INSTRUCTION CACHE 有权

    公开(公告)号：US20140372736A1

    公开(公告)日：2014-12-18

    申请号：US14301991

    申请日：2014-06-11

    Applicant: ARM LIMITED

    Inventor： Peter Richard GREENHALGH

    IPC: G06F9/38

    CPC classification number: G06F9/3806 ,  G06F9/3804 ,  G06F9/3869

    Abstract: A data processing apparatus and method are provided for handling retrieval of instructions from an instruction cache. Fetch circuitry retrieves instructions from the instruction cache into a temporary buffer, and execution circuitry executes a sequence of instructions retrieved from the temporary buffer, that sequence including branch instructions. Branch prediction circuitry is configured to predict, for each identified branch instruction in the sequence, if that branch instruction will result in a taken branch when that branch instruction is subsequently executed by the execution circuitry. In a normal operating mode, the fetch circuitry retrieves one or more speculative instructions from the instruction cache between the time that a source branch instruction is retrieved from the instruction cache and the branch prediction circuitry predicts if that source branch instruction will result in the taken branch. In the event that that source branch instruction is predicted as taken, the one or more speculative instructions are discarded. In the event that a source branch instruction is predicted as taken, throttle prediction circuitry maintains a count value indicative of a number of instructions appearing in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction, that is predicted as taken, the throttle prediction circuitry operates the fetch circuitry in a throttled mode where the number of instructions subsequently retrieved by the fetch circuitry from the instruction cache is limited dependent on the count value, and then the fetch circuitry is prevented from retrieving any further instructions from the instruction cache for a predetermined number of clock cycles. This serves to reduce the power consumption consumed in accessing the instruction cache to retrieve speculative instructions which later need to be discarded.

    PROCESSOR AND METHOD FOR PROCESSING INSTRUCTIONS USING AT LEAST ONE PROCESSING PIPELINE
    9.
    发明申请
    PROCESSOR AND METHOD FOR PROCESSING INSTRUCTIONS USING AT LEAST ONE PROCESSING PIPELINE 有权
    用于处理使用至少一个加工管道的说明书的处理器和方法

    公开(公告)号：US20140281423A1

    公开(公告)日：2014-09-18

    申请号：US13826553

    申请日：2013-03-14

    Applicant: ARM LIMITED

    Inventor： Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Max John BATLEY

    IPC: G06F9/30

    CPC classification number: G06F9/30079 ,  G06F9/3836 ,  G06F9/3875 ,  G06F9/3885

    Abstract: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource and can be processed using the duplicated resource at either of the second and third stages, the first stage determines whether a required operand would be available when the pending instruction would reach the second stage. If the operand would be available, then the pending instruction is processed using the duplicated resource at the second stage, while if the operand would not be available in time then the instruction is processed using the duplicated resource in the third pipeline stage. This technique helps to reduce delays caused by data dependency hazards.

    Abstract translation: 处理器具有第一，第二和第三阶段的处理流水线。 第一阶段的指令需要更少的周期才能到达第二阶段，然后到第三阶段。 第二和第三阶段各有一个重复的处理资源。 对于要求复制的资源并且可以使用第二级和第三级中的任一级的重复资源来处理的等待指令，第一级确定当待命指令将到达第二级时所需的操作数是否可用。 如果操作数可用，则在第二阶段使用重复的资源处理挂起的指令，而如果操作数在时间上不可用，则使用第三流水线阶段中的重复资源处理指令。 这种技术有助于减少数据依赖性危害造成的延误。

    CACHE CONTROL IN PRESENCE OF SPECULATIVE READ OPERATIONS
    10.
    发明申请
    CACHE CONTROL IN PRESENCE OF SPECULATIVE READ OPERATIONS 有权

    公开(公告)号：US20210042227A1

    公开(公告)日：2021-02-11

    申请号：US16979624

    申请日：2019-03-12

    Applicant: Arm Limited

    Inventor： Andreas Lars SANDBERG ,  Stephan DIESTELHORST ,  Nikos NIKOLERIS ,  Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Frederic Claude Marie PIRY ,  Albin Pierrick TONNERRE

    IPC: G06F12/0802

    Abstract: Coherency control circuitry (10) supports processing of a safe-speculative-read transaction received from a requesting master device (4). The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache (11) of the requesting master device (4) while prohibiting any change in coherency state associated with the target data in other caches (12) in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry (10) and the second cache (12) is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.

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