公开(公告)号：US20140181768A1

公开(公告)日：2014-06-26

申请号：US13723279

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Jian Yang ,  Pingping Shao ,  Houkun Li ,  Jerry Su ,  Chi Tang ,  Griffin Wang

IPC: G06F17/50

CPC classification number: G06F17/5081

Abstract: A method and apparatus for automated performance verification for integrated circuit design is described herein. The method includes test preparation and automated verification stages. The test preparation stage generates design feature-specific performance tests to meet expected performance goals under certain workloads using optimization approaches and for different design configurations. The automated verification stage is implemented by integrating functional, automated modules into a verification infrastructure. These modules include register transfer level (RTL) simulation, performance evaluation and performance publish modules. The RTL simulation module schedules performance testing jobs, runs a series of performance tests on simulation logic simultaneously and generates performance counters for each functional unit. The performance evaluation module consists of three sub-functions including a functional comparison between actual results and a reference file containing the expected results, performance measurements for throughput, execution time, and latency values, and performance analysis. The performance publish module publishes performance results and analysis reports.

Abstract translation: 本文描述了用于集成电路设计的自动化性能验证的方法和装置。 该方法包括测试准备和自动验证阶段。 测试准备阶段通过使用优化方法和不同的设计配置，在某些工作负载下生成设计特征性能测试，以满足预期的性能目标。 通过将功能自动化模块集成到验证基础设施中来实现自动化验证阶段。 这些模块包括注册传输级别（RTL）模拟，性能评估和性能发布模块。 RTL仿真模块调度性能测试作业，同时对仿真逻辑进行一系列性能测试，并为每个功能单元生成性能计数器。 性能评估模块包括三个子功能，包括实际结果与包含预期结果的参考文件，吞吐量性能测量，执行时间和延迟值以及性能分析之间的功能比较。 性能发布模块发布性能结果和分析报告。

公开(公告)号：US11983560B2

公开(公告)日：2024-05-14

申请号：US17571374

申请日：2022-01-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Li Peng ,  Jian Yang ,  Chi Tang

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/0815 ,  G06F12/084 ,  G06F15/78

CPC classification number: G06F9/4881 ,  G06F9/542 ,  G06F12/0815 ,  G06F12/084 ,  G06F15/7807

Abstract: Systems, apparatuses, and methods for efficient parallel execution of multiple work units in a processor by reducing a number of memory accesses are disclosed. A computing system includes a processor core with a parallel data architecture. One or more of a software application and firmware implement matrix operations and support the broadcast of shared data to multiple compute units of the processor core. The application creates thread groups by matching compute kernels of the application with data items, and grouping the resulting work units into thread groups. The application assigns the thread groups to compute units based on detecting shared data among the compute units. Rather than send multiple read access to a memory subsystem for the shared data, a single access request is generated. The single access request includes information to identify the multiple compute units for receiving the shared data when broadcasted.

公开(公告)号：US20130169636A1

公开(公告)日：2013-07-04

申请号：US13688853

申请日：2012-11-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Jian Yang ,  Huaibing Zhu ,  Vineet Goel ,  Yan Li

IPC: G06T15/08

CPC classification number: G06T15/08 ,  G06T15/04 ,  G06T17/20 ,  G06T17/205

Abstract: A system, method, and computer program product are provided for tessellation using shaders. New graphics pipeline stages implemented by shaders are introduced, including an inner ring shader, an outer edge shader, and topologic shader, which work together with a domain shader and geometry shader to provide tessellated points and primitives. A hull shader is modified to compute values used by the new shaders to perform tessellation algorithms. This approach provides parallelism and customizability to the presently static tessellation engine implementation.

Abstract translation: 提供了使用着色器进行细分的系统，方法和计算机程序产品。 引入了由着色器实现的新图形流水线阶段，包括内环着色器，外边缘着色器和拓扑着色器，它们与域着色器和几何着色器一起工作，以提供细分点和基元。 修改船体着色器以计算新着色器使用的值来执行镶嵌算法。 这种方法提供了对当前静态细分引擎实现的并行性和可定制性。