公开(公告)号：US20230143760A1

公开(公告)日：2023-05-11

申请号：US17521483

申请日：2021-11-08

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F12/084 ,  G06F12/0811 ,  G06F12/0868

CPC classification number: G06F12/084 ,  G06F12/0811 ,  G06F12/0868

Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.

公开(公告)号：US11483209B2

公开(公告)日：2022-10-25

申请号：US16688814

申请日：2019-11-19

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Kartik Shenoy

IPC: H04L41/12 ,  H04L43/0894

Abstract: A communication network includes: a plurality of nodes in a topology, with each node having an upstream and a downstream neighboring node in the topology; a separate unidirectional communication link coupled between each node and that node's downstream neighboring node; and a separate unidirectional control link coupled between each node and that node's upstream neighboring node. A controller in each node keeps a count of packets sent by that node via the corresponding unidirectional communication link. The controller uses the count of packets sent to determine whether a given packet is allowed to be sent from that node to the downstream neighboring node and, if so, whether a full rate or a throttled rate is to be used for sending the given packet. Based at least in part on the determining, the controller selectively sends the given packet to the downstream neighboring node.

公开(公告)号：US20220188229A1

公开(公告)日：2022-06-16

申请号：US17118612

申请日：2020-12-11

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley

IPC: G06F12/084 ,  G06F12/128 ,  G06F12/126 ,  G06F11/30

Abstract: A method includes monitoring one or more metrics for each of a plurality of cache users sharing a cache, and assigning each of the plurality of cache users to one of a plurality of groups based on the monitored one or more metrics.

公开(公告)号：US20210406145A1

公开(公告)日：2021-12-30

申请号：US17004589

申请日：2020-08-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kelley ,  Paul Moyer

IPC: G06F11/30 ,  G06F11/34 ,  G06F11/07 ,  G06F12/0891 ,  G06F12/0804

Abstract: An electronic device includes a cache with a cache controller and a cache memory. The electronic device also includes a cache policy manager. The cache policy manager causes the cache controller to use two or more cache policies for cache operations in each of multiple test regions in the cache memory, with different configuration values for the two or more cache policies being used in each test region. The cache policy manager selects a selected configuration value for at least one cache policy of the two or more cache policies based on performance metrics for cache operations while using the different configuration values for the two or more cache policies in the test regions. The cache policy manager causes the cache controller to use the selected configuration value when using the at least one cache policy for cache operations in a main region of the cache memory.

公开(公告)号：US11210234B2

公开(公告)日：2021-12-28

申请号：US16669973

申请日：2019-10-31

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul Moyer ,  John Kelley

IPC: G06F12/12

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

公开(公告)号：US11880310B2

公开(公告)日：2024-01-23

申请号：US17553044

申请日：2021-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Paul Moyer ,  John Kelley

IPC: G06F12/12

CPC classification number: G06F12/12 ,  G06F2212/601

Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.