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公开(公告)号:US10534721B2
公开(公告)日:2020-01-14
申请号:US15790616
申请日:2017-10-23
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Paul Moyer
IPC: G06F12/128 , G06F12/0811 , G06F12/126 , G06F12/127 , G06F12/0875
Abstract: A cache controller determines replacement priority for cache lines at a cache based on data stored at non-cache buffers. In response to determining that a cache line at the cache is to be replaced, the cache controller identifies a set of candidate cache lines for replacement. The cache controller probes the non-cache buffers to identify any entries that are assigned to the same memory address as a candidate cache line and adjusts the replacement priorities for the candidate cache lines based on the probe responses. The cache controller deprioritizes for replacement cache lines associated with entries of the non-cache buffers.
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公开(公告)号:US10509732B2
公开(公告)日:2019-12-17
申请号:US15139923
申请日:2016-04-27
Applicant: Advanced Micro Devices, Inc.
Inventor: Paul Moyer
IPC: G06F12/00 , G06F12/123 , G06F12/0862
Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.
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公开(公告)号:US12153926B2
公开(公告)日:2024-11-26
申请号:US18393657
申请日:2023-12-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: John Kalamatianos , Michael T. Clark , Marius Evers , William L. Walker , Paul Moyer , Jay Fleischman , Jagadish B. Kotra
Abstract: Processor-guided execution of offloaded instructions using fixed function operations is disclosed. Instructions designated for remote execution by a target device are received by a processor. Each instruction includes, as an operand, a target register in the target device. The target register may be an architected virtual register. For each of the plurality of instructions, the processor transmits an offload request in the order that the instructions are received. The offload request includes the instruction designated for remote execution. The target device may be, for example, a processing-in-memory device or an accelerator coupled to a memory.
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公开(公告)号:US11924338B2
公开(公告)日:2024-03-05
申请号:US17089493
申请日:2020-11-04
Applicant: Advanced Micro Devices, Inc.
Inventor: David A Kaplan , Paul Moyer
CPC classification number: H04L9/0869 , G06F7/58 , G06F7/588
Abstract: A computing system may implement a split random number generator that may use a random number generator to generate and store seed values in a memory for retrieval and use by one or more core processors to generate random numbers for secure processes within each core processor.
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公开(公告)号:US11880310B2
公开(公告)日:2024-01-23
申请号:US17553044
申请日:2021-12-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: Paul Moyer , John Kelley
IPC: G06F12/12
CPC classification number: G06F12/12 , G06F2212/601
Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.
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公开(公告)号:US20170315932A1
公开(公告)日:2017-11-02
申请号:US15139923
申请日:2016-04-27
Applicant: Advanced Micro Devices, Inc.
Inventor: Paul Moyer
IPC: G06F12/123 , G06F12/0862
CPC classification number: G06F12/123 , G06F12/0862 , G06F2212/1021 , G06F2212/602
Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.
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公开(公告)号:US11803484B2
公开(公告)日:2023-10-31
申请号:US17512943
申请日:2021-10-28
Applicant: Advanced Micro Devices, Inc.
Inventor: Paul Moyer
IPC: G06F12/123 , G06F12/0862 , G06F12/0888 , G06F12/12
CPC classification number: G06F12/123 , G06F12/0862 , G06F12/0888 , G06F12/12 , G06F2212/1016 , G06F2212/502 , G06F2212/6028
Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.
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公开(公告)号:US20230143760A1
公开(公告)日:2023-05-11
申请号:US17521483
申请日:2021-11-08
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: John Kelley , Paul Moyer
IPC: G06F12/084 , G06F12/0811 , G06F12/0868
CPC classification number: G06F12/084 , G06F12/0811 , G06F12/0868
Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.
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公开(公告)号:US20220114123A1
公开(公告)日:2022-04-14
申请号:US17068660
申请日:2020-10-12
Applicant: Advanced Micro Devices, Inc.
Inventor: Bryan P Broussard , Paul Moyer , Eric Christopher Morton , Pravesh Gupta
IPC: G06F13/26 , G06F13/40 , G06F12/0875
Abstract: A method of operating a processing unit includes storing a first copy of a first interrupt control value in a cache device of the processing unit, receiving from an interrupt controller a first interrupt message transmitted via an interconnect fabric, where the first interrupt message includes a second copy of the first interrupt control value, and if the first copy matches the second copy, servicing an interrupt specified in the first interrupt message.
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公开(公告)号:US20220075736A1
公开(公告)日:2022-03-10
申请号:US17512943
申请日:2021-10-28
Applicant: Advanced Micro Devices, Inc.
Inventor: Paul Moyer
IPC: G06F12/123 , G06F12/0862 , G06F12/0888
Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.
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