Cache replacement policy based on non-cache buffers

    公开(公告)号:US10534721B2

    公开(公告)日:2020-01-14

    申请号:US15790616

    申请日:2017-10-23

    Inventor: Paul Moyer

    Abstract: A cache controller determines replacement priority for cache lines at a cache based on data stored at non-cache buffers. In response to determining that a cache line at the cache is to be replaced, the cache controller identifies a set of candidate cache lines for replacement. The cache controller probes the non-cache buffers to identify any entries that are assigned to the same memory address as a candidate cache line and adjusts the replacement priorities for the candidate cache lines based on the probe responses. The cache controller deprioritizes for replacement cache lines associated with entries of the non-cache buffers.

    Selecting cache aging policy for prefetches based on cache test regions

    公开(公告)号:US10509732B2

    公开(公告)日:2019-12-17

    申请号:US15139923

    申请日:2016-04-27

    Inventor: Paul Moyer

    Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.

    Cache access measurement deskew
    5.
    发明授权

    公开(公告)号:US11880310B2

    公开(公告)日:2024-01-23

    申请号:US17553044

    申请日:2021-12-16

    CPC classification number: G06F12/12 G06F2212/601

    Abstract: A processor includes a cache having two or more test regions and a larger non-test region. The processor further includes a cache controller that applies different cache replacement policies to the different test regions of the cache, and a performance monitor that measures performance metrics for the different test regions, such as a cache hit rate at each test region. Based on the performance metrics, the cache controller selects a cache replacement policy for the non-test region, such as selecting the replacement policy associated with the test region having the better performance metrics among the different test regions. The processor deskews the memory access measurements in response to a difference in the amount of accesses to the different test regions exceeding a threshold.

    Selecting Cache Aging Policy For Prefetches Based on Cache Test Regions

    公开(公告)号:US20170315932A1

    公开(公告)日:2017-11-02

    申请号:US15139923

    申请日:2016-04-27

    Inventor: Paul Moyer

    CPC classification number: G06F12/123 G06F12/0862 G06F2212/1021 G06F2212/602

    Abstract: A cache controller applies an aging policy to a portion of a cache based on access metrics for different test regions of the cache, whereby each test region implements a different aging policy. The aging policy for each region establishes an initial age value for each entry of the cache, and a particular aging policy can set the age for a given entry based on whether the entry was placed in the cache in response to a demand request from a processor core or in response to a prefetch request. The cache controller can use the age value of each entry as a criterion in its cache replacement policy.

    COMPUTER PROCESSING DEVICES WITH DYNAMIC SHARED CACHE LINE COPY RETENTION POLICY SELECTION

    公开(公告)号:US20230143760A1

    公开(公告)日:2023-05-11

    申请号:US17521483

    申请日:2021-11-08

    CPC classification number: G06F12/084 G06F12/0811 G06F12/0868

    Abstract: Systems and techniques for dynamic selection of policy that determines whether copies of shared cache lines in a processor core complex are to be stored and maintained in a level 3 (L3) cache of the processor core complex are based on one or more cache line sharing parameters or based on a counter that tracks L3 cache misses and cache-to-cache (C2C) transfers in the processor core complex, according to various embodiments. Shared cache lines are shared between processor cores or between threads. By comparing either the cache line sharing parameters or the counter to corresponding thresholds, a policy is set which defines whether copies of shared cache lines at such indices are to be retained in the L3 cache.

    DYNAMIC APPLICATION OF SOFTWARE DATA CACHING HINTS BASED ON CACHE TEST REGIONS

    公开(公告)号:US20220075736A1

    公开(公告)日:2022-03-10

    申请号:US17512943

    申请日:2021-10-28

    Inventor: Paul Moyer

    Abstract: A processor applies a software hint policy to a portion of a cache based on access metrics for different test regions of the cache, wherein each test region applies a different software hint policy for data associated with cache entries in each region of the cache. One test region applies a software hint policy under which software hints are followed. The other test region applies a software hint policy under which software hints are ignored. One of the software hint policies is selected for application to a non-test region of the cache.

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