公开(公告)号：US11847062B2

公开(公告)日：2023-12-19

申请号：US17552703

申请日：2021-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tarun Nakra ,  Jay Fleischman ,  Gautam Tarasingh Hazari ,  Akhil Arunkumar ,  William L. Walker ,  Gabriel H. Loh ,  John Kalamatianos ,  Marko Scrbak

IPC: G06F12/0897 ,  G06F12/0891

CPC classification number: G06F12/0897 ,  G06F12/0891 ,  G06F2212/1028

Abstract: In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.

公开(公告)号：US20230195643A1

公开(公告)日：2023-06-22

申请号：US17552703

申请日：2021-12-16

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Tarun Nakra ,  Jay Fleischman ,  Gautam Tarasingh Hazari ,  Akhil Arunkumar ,  William L. Walker ,  Gabriel H. Loh ,  John Kalamatianos ,  Marko Scrbak

IPC: G06F12/0897 ,  G06F12/0891

CPC classification number: G06F12/0897 ,  G06F12/0891 ,  G06F2212/1028

Abstract: In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.

公开(公告)号：US20140310506A1

公开(公告)日：2014-10-16

申请号：US13861083

申请日：2013-04-11

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： David A Kaplan ,  Daniel Hopper ,  Tarun Nakra

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838

Abstract: The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction.

Abstract translation: 本发明提供了一种用于分配存储队列条目以存储用于早期存储到负载转发的指令的方法和装置。 该方法的一些实施例包括响应于调度的存储指令以及在将虚拟地址转换为与存储指令相关联的物理地址之前，将存储队列中的条目分配到存储指令到存储指令。 该条目包括通过存储指令写入物理地址的数据的存储。

公开(公告)号：US20140189245A1

公开(公告)日：2014-07-03

申请号：US13731292

申请日：2012-12-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Jeff Rupley ,  Tarun Nakra

IPC: G06F12/12

CPC classification number: G06F12/0811 ,  G06F5/065 ,  G06F12/0808 ,  G06F13/1673

Abstract: A processor includes a first cache memory and a bus unit in some embodiments. The bus unit includes a plurality of buffers and is operable to allocate a selected buffer of a plurality of buffers for a fill request associated with a first cache line to be stored in a first cache memory, load fill data from the first cache line into the selected buffer, and transfer the fill data to the first cache memory in parallel with storing eviction data for an evicted cache line from the first cache memory in the selected buffer.

Abstract translation: 在一些实施例中，处理器包括第一高速缓冲存储器和总线单元。 总线单元包括多个缓冲器，并且可操作以分配用于与要存储在第一高速缓冲存储器中的第一高速缓存行相关联的填充请求的多个缓冲器的选定缓冲器，将填充数据从第一高速缓存行加载到 并且将填充数据与从所选择的缓冲器中的第一高速缓冲存储器中取出的驱逐规则数据并行地传送到第一缓存存储器。