公开(公告)号：US20140317356A1

公开(公告)日：2014-10-23

申请号：US13864542

申请日：2013-04-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Sriram Srinivasan ,  Tarun Nakra

IPC分类号： G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0844 ,  G06F12/0857 ,  Y02D10/13

摘要： A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.

摘要翻译： 处理器包括处理单元，高速缓冲存储器和中央请求队列。 中央请求队列可操作以接收用于要加载到高速缓存存储器中的高速缓存行的预取加载请求，从处理单元接收对高速缓存行的请求加载请求，合并预取加载请求和请求加载请求以生成 指定处理单元作为请求者的升级加载请求，接收与所提升的加载请求相关联的高速缓存行，并将高速缓存行转发到处理单元。

公开(公告)号：US20230195628A1

公开(公告)日：2023-06-22

申请号：US17558034

申请日：2021-12-21

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Akhil Arunkumar ,  Tarun Nakra ,  Maxim V. Kazakov ,  Milind N. Nemlekar

IPC分类号： G06F12/0811 ,  G06F12/0853 ,  G06F13/16

CPC分类号： G06F12/0811 ,  G06F12/0853 ,  G06F13/1642 ,  G06F13/1668

摘要： Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.

公开(公告)号：US11580025B1

公开(公告)日：2023-02-14

申请号：US17490529

申请日：2021-09-30

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Tarun Nakra ,  Akhil Arunkumar ,  Vydhyanathan Kalyanasundharam ,  Chintan S. Patel ,  Nithesh Kurella Lakshmi Narayanamurthy

IPC分类号： G06F12/0862

摘要： Systems and methods for coordinated memory-side cache prefetching and dynamic interleaving configuration modification involve modifying one or both of the prefetch distance or the prefetch degree used by prefetcher modules of one or more memory-side caches by modifying interleaving configuration data following detection of an interleaving reconfiguration trigger condition indicative, for example, of low prefetch accuracy, low prefetch coverage, high prefetch lateness, or a combination of these. In response an interleaving reconfiguration trigger condition, a processor modifies the interleaving configuration data for the processing system based on the prefetch performance characteristics associated with the interleaving reconfiguration trigger condition. In some embodiments, the interleaving configuration data is modified by changing which physical memory address indices are used to determine the bits that define the channel identification number to which that physical memory address is to be mapped.

公开(公告)号：US09213640B2

公开(公告)日：2015-12-15

申请号：US13864844

申请日：2013-04-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： David A. Kaplan ,  Tarun Nakra

IPC分类号： G06F12/14 ,  G06F12/08

CPC分类号： G06F12/0802 ,  G06F12/0862

摘要： A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel.

摘要翻译： 处理器包括高速缓存存储器，包括指令执行单元的第一核心以及将高速缓冲存储器耦合到第一核心的存储器总线。 存储器总线可操作以接收用于高速缓冲存储器的数据的高速缓存行的第一部分，第一核可操作以识别针对高速缓存行和第一部分的多个数据请求，并选择所识别的多个数据之一 请求执行，并且存储器总线可操作以并行地将第一部分转发到指令执行单元和高速缓冲存储器。

公开(公告)号：US20140317357A1

公开(公告)日：2014-10-23

申请号：US13864844

申请日：2013-04-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： David A. Kaplan ,  Tarun Nakra

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F12/0862

摘要： A processor includes a cache memory, a first core including an instruction execution unit, and a memory bus coupling the cache memory to the first core. The memory bus is operable to receive a first portion of a cache line of data for the cache memory, the first core is operable to identify a plurality of data requests targeting the cache line and the first portion and select one of the identified plurality of data requests for execution, and the memory bus is operable to forward the first portion to the instruction execution unit and to the cache memory in parallel.

摘要翻译： 处理器包括高速缓存存储器，包括指令执行单元的第一核心以及将高速缓冲存储器耦合到第一核心的存储器总线。 存储器总线可操作以接收用于高速缓冲存储器的数据的高速缓存行的第一部分，第一核可操作以识别针对高速缓存行和第一部分的多个数据请求，并选择所识别的多个数据之一 请求执行，并且存储器总线可操作以并行地将第一部分转发到指令执行单元和高速缓冲存储器。

公开(公告)号：US09335999B2

公开(公告)日：2016-05-10

申请号：US13861083

申请日：2013-04-11

申请人： ADVANCED MICRO DEVICES, INC.

发明人： David A Kaplan ,  Daniel Hopper ,  Tarun Nakra

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838

摘要： The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction.

摘要翻译： 本发明提供了一种用于分配存储队列条目以存储用于早期存储到负载转发的指令的方法和装置。 该方法的一些实施例包括响应于调度的存储指令以及在将虚拟地址转换为与存储指令相关联的物理地址之前，将存储队列中的条目分配到存储指令到存储指令。 该条目包括通过存储指令写入物理地址的数据的存储。

公开(公告)号：US09286223B2

公开(公告)日：2016-03-15

申请号：US13864542

申请日：2013-04-17

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Sriram Srinivasan ,  Tarun Nakra

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0844 ,  G06F12/0857 ,  Y02D10/13

摘要： A processor includes a processing unit, a cache memory, and a central request queue. The central request queue is operable to receive a prefetch load request for a cache line to be loaded into the cache memory, receive a demand load request for the cache line from the processing unit, merge the prefetch load request and the demand load request to generate a promoted load request specifying the processing unit as a requestor, receive the cache line associated with the promoted load request, and forward the cache line to the processing unit.

摘要翻译： 处理器包括处理单元，高速缓冲存储器和中央请求队列。 中央请求队列可操作以接收用于要加载到高速缓存存储器中的高速缓存行的预取加载请求，从处理单元接收对高速缓存行的请求加载请求，合并预取加载请求和请求加载请求以生成 指定处理单元作为请求者的升级加载请求，接收与所提升的加载请求相关联的高速缓存行，并将高速缓存行转发到处理单元。

公开(公告)号：US20140129776A1

公开(公告)日：2014-05-08

申请号：US13667095

申请日：2012-11-02

申请人： ADVANCED MICRO DEVICES, INC.

发明人： David A. Kaplan ,  Jeff Rupley ,  Tarun Nakra

IPC分类号： G06F12/08

CPC分类号： G06F9/30065 ,  G06F9/30043 ,  G06F9/3861 ,  G06F12/0802 ,  G06F12/0815

摘要： A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.

摘要翻译： 提供了一种用于执行可缓存存储的方法。 该方法包括基于高速缓存行的状态和存储指令的执行阶段确定是否重放存储指令以重新获取一个或多个高速缓存行。 响应于确定重播商店指令而重放存储指令。 提供了一种装置，其包括可配置以基于高速缓存行的状态和存储指令的执行阶段来确定是否重播存储指令以重新获取一个或多个高速缓存行的存储队列（SQ）。 提供了用于使制造设备适应制造装置的计算机可读存储装置。

公开(公告)号：US11960399B2

公开(公告)日：2024-04-16

申请号：US17558034

申请日：2021-12-21

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Akhil Arunkumar ,  Tarun Nakra ,  Maxim V. Kazakov ,  Milind N. Nemlekar

IPC分类号： G06F12/0811 ,  G06F12/0853 ,  G06F13/16

CPC分类号： G06F12/0811 ,  G06F12/0853 ,  G06F13/1642 ,  G06F13/1668

摘要： Methods, systems, and devices maintain state information in a shadow tag memory for a plurality of cachelines in each of a plurality of private caches, with each of the private caches being associated with a corresponding one of multiple processing cores. One or more cache probes are generated based on a write operation associated with one or more cachelines of the plurality of cachelines, such that each of the cache probes is associated with cachelines of a particular private cache of the multiple private caches, the particular private cache being associated with an indicated processing core. Transmission of the cache probes to the particular private cache is prevented until, responsive to a scope acquire operation from the indicated processing core, the cache probes are released for transmission to the respectively associated cachelines in the particular private cache.

公开(公告)号：US11847062B2

公开(公告)日：2023-12-19

申请号：US17552703

申请日：2021-12-16

申请人： ADVANCED MICRO DEVICES, INC.

发明人： Tarun Nakra ,  Jay Fleischman ,  Gautam Tarasingh Hazari ,  Akhil Arunkumar ,  William L. Walker ,  Gabriel H. Loh ,  John Kalamatianos ,  Marko Scrbak

IPC分类号： G06F12/0897 ,  G06F12/0891

CPC分类号： G06F12/0897 ,  G06F12/0891 ,  G06F2212/1028

摘要： In response to eviction of a first clean data block from an intermediate level of cache in a multi-cache hierarchy of a processing system, a cache controller accesses an address of the first clean data block. The controller initiates a fetch of the first clean data block from a system memory into a last-level cache using the accessed address.