公开(公告)号：US07363532B2

公开(公告)日：2008-04-22

申请号：US10923119

申请日：2004-08-20

申请人： Ahmad A. J. Ali ,  Rohit Chawla ,  Gary B. Kotzur ,  Kevin T. Marks ,  Howard A. Shoobe

发明人： Ahmad A. J. Ali ,  Rohit Chawla ,  Gary B. Kotzur ,  Kevin T. Marks ,  Howard A. Shoobe

IPC分类号： G06F11/00

CPC分类号： G06F11/1092 ,  G06F11/1662 ,  G06F11/2094

摘要： A system and method for recovering from a drive failure in a storage array is disclosed in which a spare drive array is provided in the event of a failure in one of the active drives of the storage array. The spare drive array is comprised of multiple drives that are comprised in a RAID 0 configuration to reduce the time required to rebuild the content of the failed drive on the spare drive.

摘要翻译： 公开了一种用于从存储阵列中的驱动器故障中恢复的系统和方法，其中在存储阵列的一个有效驱动器中的一个故障的情况下提供备用驱动器阵列。 备用驱动器阵列由包含在RAID 0配置中的多个驱动器组成，以减少重新构建备用驱动器上的故障驱动器内容所需的时间。

公开(公告)号：US6098109A

公开(公告)日：2000-08-01

申请号：US774601

申请日：1996-12-30

申请人： Gary B. Kotzur ,  Patricia E. Hareski ,  Michael L. Witkowski ,  Dale J. Mayer ,  William J. Walker

发明人： Gary B. Kotzur ,  Patricia E. Hareski ,  Michael L. Witkowski ,  Dale J. Mayer ,  William J. Walker

IPC分类号： G06F15/16 ,  G06F13/362 ,  G06F15/17 ,  G06F15/177 ,  H04L12/56 ,  G06F3/00 ,  H04L12/28

CPC分类号： H04L49/254 ,  H04L45/745 ,  H04L49/205 ,  H04L49/351 ,  Y10S370/911

摘要： A programmable arbitration system including control logic to select one of several arbitration schemes for selecting the ports of a network switch, a memory to store priority values indicating the relative priority of each of the ports, monitor logic to monitor each of the ports and to program the priority values in the memory based on a priority scheme selected by the control logic, and arbitration logic to select a port having the next highest priority. The arbitration schemes preferably include a round-robin priority scheme, a first-come, first-served (FCFS) priority scheme, a weighted priority scheme, or any other desirable priority scheme. The monitor logic includes polling logic to periodically poll the ports and to program a priority value of each port. The memory includes receive and transmit lists to indicate of which of the ports have indicated needing service and a corresponding priority value. The arbitration logic includes a receive arbiter and a transmit arbiter, each of which use a corresponding arbitration count.

公开(公告)号：US5862338A

公开(公告)日：1999-01-19

申请号：US774602

申请日：1996-12-30

申请人： William J. Walker ,  Gary B. Kotzur ,  Michael L. Witkowski ,  Patricia E. Hareski ,  Dale J. Mayer

发明人： William J. Walker ,  Gary B. Kotzur ,  Michael L. Witkowski ,  Patricia E. Hareski ,  Dale J. Mayer

IPC分类号： G06F13/00 ,  H04L12/403 ,  H04L12/56 ,  G06F17/00

CPC分类号： H04L49/351 ,  H04L49/254 ,  H04L49/354

摘要： A multiport polling system for a network switch including a plurality of network ports, each including receive and transmit buffers. Each port includes port status logic for providing status signals indicative of whether a corresponding port has received data from a network device and whether a corresponding port has available space to receive data to transmit to a network device. The network switch further includes a switch manager for controlling data flow between the ports. The switch manager includes polling logic for periodically polling the port status logic of each port for receiving the status signals, and a memory for storing values indicative of the status signals for each port. In this manner, all of the ports are simultaneously polled in a singe query and the receive and transmit status of each port is maintained in the memory. This facilitates arbitration and control logic, which continuously reviews the memory to determine when to retrieve data from a source port and when to transmit data to one or more destination ports. The ports are preferably implemented with quad cascade devices for providing multiplexed status signals.

摘要翻译： 一种用于包括多个网络端口的网络交换机的多端口轮询系统，每个网络端口包括接收和发送缓冲器。 每个端口包括端口状态逻辑，用于提供表示相应端口是否已经从网络设备接收到数据的状态信号，以及对应的端口是否具有用于接收数据以发送到网络设备的可用空间。 网络交换机还包括用于控制端口之间的数据流的交换管理器。 交换机管理器包括用于周期性地轮询每个端口的端口状态逻辑以接收状态信号的轮询逻辑，以及用于存储指示每个端口的状态信号的值的存储器。 以这种方式，所有端口同时轮询单个查询，并且每个端口的接收和发送状态保持在存储器中。 这有助于仲裁和控制逻辑，其不断地审查存储器以确定何时从源端口检索数据以及何时将数据发送到一个或多个目的地端口。 这些端口优选地用用于提供多路复用状态信号的四级级联装置来实现。

公开(公告)号：US5495569A

公开(公告)日：1996-02-27

申请号：US366778

申请日：1994-12-30

申请人： Gary B. Kotzur

发明人： Gary B. Kotzur

IPC分类号： G06F11/00 ,  G06F11/20 ,  G06F11/22

CPC分类号： G06F11/0757 ,  G06F11/0724 ,  G06F11/20 ,  G06F11/22

摘要： A hot spare boot circuit that automatically switches from a non-operational CPU to an operational CPU for powering up the computer system. In the multiprocessor computer system, a first CPU is designated to perform power on operations. If the first CPU fails, which is determined when a dead man counter in the hot spare boot circuit times out, the hot spare circuit ensures that the first CPU is in a disabled state. Next, the hot spare boot circuit identifies an operational second CPU, reinitializing certain ID information as necessary such that the second CPU can properly perform power on operations. The hot spare boot then awakens the second CPU, using a startup interprocessor interrupt in one embodiment, or simply negating the hard reset of the second CPU in a second embodiment. The second CPU then proceeds to perform the power on functions.

摘要翻译： 一个热备用引导电路，可自动从非操作CPU切换到运行CPU，以便为计算机系统供电。 在多处理器计算机系统中，指定第一CPU执行上电操作。 如果第一个CPU出现故障，当热备用引导电路中的死亡计数器超时时确定，热备用电路确保第一个CPU处于禁用状态。 接下来，热备用引导电路识别操作的第二CPU，根据需要重新初始化某些ID信息，使得第二CPU可以正常地执行上电操作。 热备用引导然后在一个实施例中唤醒第二CPU，使用启动处理器中断，或者在第二实施例中简单地否定第二CPU的硬复位。 然后第二个CPU继续执行上电功能。

公开(公告)号：US08954651B2

公开(公告)日：2015-02-10

申请号：US13295720

申请日：2011-11-14

申请人： Gary B. Kotzur ,  William Price Dawkins

发明人： Gary B. Kotzur ,  William Price Dawkins

IPC分类号： G06F12/00 ,  G11C16/10 ,  G11C16/34

CPC分类号： G06F3/0638 ,  G06F3/0616 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/349

摘要： A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode.

摘要翻译： 方法可以包括接收要存储在存储资源上的数据页面。 该方法还可以包括针对多个反转模式的每个特定反转模式确定要反转的数据页面的比特数，以根据特定反转模式存储数据页面的表示。 该方法可以另外包括从用于数据页的多个反转模式确定所选择的反转模式，所选择的反转模式包括需要最少数量的物理位转换以存储数据页面的表示的反转模式 根据所选择的反转模式。 该方法还可以包括根据反转模式将数据页面的表示存储在数据存储器中。

公开(公告)号：US20130124779A1

公开(公告)日：2013-05-16

申请号：US13295720

申请日：2011-11-14

申请人： Gary B. Kotzur ,  William Price Dawkins

发明人： Gary B. Kotzur ,  William Price Dawkins

IPC分类号： G06F12/00

CPC分类号： G06F3/0638 ,  G06F3/0616 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/2022 ,  G06F2212/7211 ,  G11C16/10 ,  G11C16/349

摘要： A method may comprise receiving a page of data to be stored on a storage resource. The method may also comprise determining, for each particular inversion mode of a plurality of inversion modes, the number of bits of the page of data to be inverted to store a representation of the page of data in accordance with the particular inversion mode. The method may additionally comprise determining a selected inversion mode from the plurality of inversion modes for the page of data, the selected inversion mode comprising the inversion mode for which the least number of physical bit transitions are required to store the representation of the page of data in accordance with the selected inversion mode. The method may further comprise storing the representation of the page of data in a data memory in accordance with the inversion mode.

公开(公告)号：US08312177B2

公开(公告)日：2012-11-13

申请号：US12890062

申请日：2010-09-24

申请人： Gary B. Kotzur ,  Chandrashekar Nelogal ,  John R. Sieber ,  Kevin T. Marks

发明人： Gary B. Kotzur ,  Chandrashekar Nelogal ,  John R. Sieber ,  Kevin T. Marks

IPC分类号： G06F3/00

CPC分类号： G06F13/385

摘要： In accordance with the present disclosure, a method for dynamically configuring a target device comprises receiving by one or more ports of a target device one or more initiator identifiers from one or more initiators. The method further comprises determining whether a plurality of ports received initiator identifiers from a common initiator. The method further comprises configuring the plurality of the ports to operate as a single, logical port if the plurality of ports received initiator identifiers from a common initiator.

摘要翻译： 根据本公开，用于动态配置目标设备的方法包括由目标设备的一个或多个端口从一个或多个启动器接收一个或多个启动器标识符。 该方法还包括确定多个端口是否从公共发起者接收到发起者标识符。 该方法还包括：如果多个端口从公共发起者接收到发起者标识符，则配置多个端口作为单个逻辑端口进行操作。

公开(公告)号：US20120239849A1

公开(公告)日：2012-09-20

申请号：US13048327

申请日：2011-03-15

申请人： Surender Brahmaroutu ,  Gary B. Kotzur

发明人： Surender Brahmaroutu ,  Gary B. Kotzur

IPC分类号： G06F13/20 ,  G06F12/00

CPC分类号： G06F11/1084 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0659 ,  G06F3/0689 ,  G06F11/2087

摘要： Systems and methods for performing RAID I/O operations in PCIe-based storage resources are disclosed. In accordance with embodiments of the present disclosure, a method for performing a read operation may be provided. The method may include overlaying memory address space of storage resources of a source logical unit for the read operation onto a destination address. The method may also include determining whether the source logical unit is a RAIDO array. The method may additionally include generating a source address in a receive buffer for each storage resource of the source logical unit if the source logical unit is a RAIDO array. The method may further include storing data received from each storage address of the logical unit at the generated source address of the receive buffer associated with such storage resource.

摘要翻译： 公开了在基于PCIe的存储资源中执行RAID I / O操作的系统和方法。 根据本公开的实施例，可以提供用于执行读取操作的方法。 该方法可以包括将用于读取操作的源逻辑单元的存储资源的存储器地址空间叠加到目的地地址上。 该方法还可以包括确定源逻辑单元是否是RAIDO阵列。 该方法还可以包括如果源逻辑单元是RAIDO阵列，则在源逻辑单元的每个存储资源的接收缓冲器中生成源地址。 该方法还可以包括将从逻辑单元的每个存储地址接收的数据存储在与这种存储资源相关联的接收缓冲器的生成源地址处。

公开(公告)号：US07542272B2

公开(公告)日：2009-06-02

申请号：US11240411

申请日：2005-09-30

申请人： Jimmy D. Pike ,  Gary B. Kotzur

发明人： Jimmy D. Pike ,  Gary B. Kotzur

IPC分类号： G06F1/16

CPC分类号： G06F1/20

摘要： A rotatable fan system and method is disclosed in which an array of paired fans is included as part of an information handling system. The array of paired fans can be rotated so that the interior fan becomes the exterior fan. The array includes an electrical switch for reversing the rotational direction of the blades of the paired fans following the rotation of the fan array.

摘要翻译： 公开了一种可旋转的风扇系统和方法，其中包括配对风扇的阵列作为信息处理系统的一部分。 配对风扇的阵列可以旋转，使内部风扇成为外部风扇。 该阵列包括用于在风扇阵列的旋转之后反转成对的风扇的叶片的旋转方向的电开关。

公开(公告)号：US06260073B1

公开(公告)日：2001-07-10

申请号：US08774605

申请日：1996-12-30

申请人： William J. Walker ,  Gary B. Kotzur ,  Patricia E. Hareski ,  Dale J. Mayer ,  Michael L. Witkowski

发明人： William J. Walker ,  Gary B. Kotzur ,  Patricia E. Hareski ,  Dale J. Mayer ,  Michael L. Witkowski

IPC分类号： G06F1516

CPC分类号： H04L49/351 ,  H04L49/201 ,  H04L49/205 ,  H04L49/254 ,  Y10S370/911

摘要： A network switch including one or more network ports for receiving and transmitting data is disclosed. The network switch also includes a processor, a switch manager, and memory. Each port includes a network interface, a data bus interface, and a processor port interface. A data bus is coupled to the data bus interface of each of the ports and the switch manager. A processor bus is coupled to a processor, the switch manager, and to the processor port interface of each of the ports. A memory bus is coupled to the memory and the switch manager. The switch manager periodically polls each of the network ports to determine the status of each port. The switch manager controls the flow of data between the network ports and memory based on the port status. The separate processor bus allows the processor to perform overhead functions, such as monitoring, determining status and configuration, without consuming valuable data bus bandwidth.

摘要翻译： 公开了一种包括用于接收和发送数据的一个或多个网络端口的网络交换机。 网络交换机还包括处理器，交换机管理器和存储器。 每个端口包括网络接口，数据总线接口和处理器端口接口。 数据总线耦合到每个端口和交换机管理器的数据总线接口。 处理器总线耦合到处理器，交换机管理器以及每个端口的处理器端口接口。 存储器总线耦合到存储器和开关管理器。 交换机管理器定期轮询每个网络端口，以确定每个端口的状态。 交换机管理器根据端口状态控制网络端口和内存之间的数据流。 单独的处理器总线允许处理器执行开销功能，例如监视，确定状态和配置，而不消耗有价值的数据总线带宽。