公开(公告)号：US08921942B2

公开(公告)日：2014-12-30

申请号：US13561990

申请日：2012-07-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L27/02

CPC分类号： H01L27/0259

摘要： Methods are provided for producing stacked electrostatic discharge (ESD) clamps. In one embodiment, the method includes providing a semiconductor substrate in which first and second serially-coupled transistors are formed. The first transistor includes a first well region having a first lateral edge partially forming the first transistor's base. The second transistor including a second well region having a second lateral edge partially forming the second transistor's base. Third and fourth well regions are formed in the first and second transistors, respectively, and extend a different distance into the substrate than do the well regions of the first and second transistors. The third well region has a third lateral edge separated from the first lateral edge by a first spacing dimension D1. The fourth well region has a fourth lateral edge separated from the second lateral edge by a second spacing dimension D2, which is different than D1.

摘要翻译： 提供了用于生产叠层静电放电（ESD）夹具的方法。 在一个实施例中，该方法包括提供形成第一和第二串联耦合晶体管的半导体衬底。 第一晶体管包括具有部分地形成第一晶体管的基极的第一侧边缘的第一阱区。 第二晶体管包括具有部分地形成第二晶体管的基极的第二横向边缘的第二阱区。 第三和第四阱区分别形成在第一和第二晶体管中，并且与第一和第二晶体管的阱区相比，延伸到衬底中的不同距离。 第三阱区域具有与第一侧边缘分开第一间隔尺寸D1的第三横向边缘。 第四阱区具有与第二侧边缘分离第二间隔尺寸D2的第四横向边缘，其不同于D1。

公开(公告)号：US08390071B2

公开(公告)日：2013-03-05

申请号：US12956686

申请日：2010-11-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L23/62 ,  H01L21/8222

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.

摘要翻译： 用于保护电路芯（24）的可堆叠静电放电（ESD）保护夹具（21）包括：具有基部接触（77）的基极区域（74,51,52,85）的双极晶体管（56,58） 以及与基部触点（77）间隔开横向距离Lbe的发射器（78）和靠近基部区域（74,51,52,85）的收集器（80,86,762）。 基部区域（74,51,52,85）包括包括基部触头（77）和发射极（78）的第一部分（51）和具有与集电器分离的侧边界（752）的第二部分（52） （86,762）由其宽度D控制钳位触发电压的击穿区域（84），第二部分（52）位于第一部分（51）和边界（752）之间。 通过增加发射极 - 基极区（74,51,52,85）的寄生电阻Rbe，例如增加Lbe或减小相对掺杂密度来改善ESD钳位（21）的损伤起始阈值电流It2 的第一部分（51）或其组合。

公开(公告)号：US08242566B2

公开(公告)日：2012-08-14

申请号：US12689666

申请日：2010-01-19

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L21/8222

CPC分类号： H01L27/0259

摘要： A stacked electrostatic discharge (ESD) protection clamp (99, 100-104) for protecting associated devices or circuits (24) comprises two or more series coupled (stacked) bipolar transistors (70, 700) whose individual trigger voltages Vt1 depend on their base-collector spacing D. A first (70-1, 700-1) of the transistors (70, 700) has a spacing DZ1 chosen within a D range Z1 whose slope (ΔVt1/ΔD) has a first value (ΔVt1/ΔD)Z1, and a second (70-2, 700-2) of the transistors (70, 700) has a spacing value D(Z2 or Z3) chosen within a D range Z2 or Z3 whose slope (ΔVt1/ΔD) has a second value (ΔVt1/ΔD)(Z2 or Z3) less than the first value (ΔVt1/ΔD)Z1. The sensitivity of the ESD stack trigger voltage Vt1STACK to base-collector spacing variations ΔD during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vt1STACK values can be obtained that are less sensitive to unavoidable manufacturing spacing variations ΔD.

摘要翻译： 用于保护相关器件或电路（24）的叠层静电放电（ESD）保护钳（99,100-104）包括两个或多个串联耦合（堆叠）双极晶体管（70,700），其各自的触发电压Vt1取决于它们的基极 - 收集器间隔D.晶体管（70,700）的第一（70-1,700-1）具有在D范围Z1内选择的间隔DZ1，其中斜率（＆Dgr; Vt1 /＆Dgr; D）具有第一值 晶体管（70,700）的第二（70-2,700-2）具有在D范围Z2或Z3内选择的间隔值D（Z2或Z3），其斜率 （＆Dgr; Vt1 /＆Dgr; D）具有小于第一值（＆Dgr; Vt1 /＆Dgr; D）Z1的第二值（＆Dgr; Vt1 /＆Dgr; D）（Z2或Z3）。 ESD堆栈触发电压Vt1STACK对制造过程中基极集电极间距变化和Dgr D的灵敏度大大降低，例如，2堆叠多达50％，3堆叠以上更多。 可以获得对不可避免的制造间距变化敏感的大范围的Vt1STACK值。

公开(公告)号：US08193560B2

公开(公告)日：2012-06-05

申请号：US12487031

申请日：2009-06-18

申请人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L29/66

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection device coupled across input-output (I/O) and common terminals of a core circuit, comprises, first and second merged bipolar transistors. A base of the first transistor serves as collector of the second transistor and the base of the second transistor serves as collector of the first transistor, the bases having, respectively, first width and second width. A first resistance is coupled between an emitter and base of the first transistor and a second resistance is coupled between an emitter and base of the second transistor. ESD trigger voltage Vtl and holding voltage Vh can be independently optimized by choosing appropriate base widths and resistances. By increasing Vh to approximately equal Vtl, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage.

摘要翻译： 耦合在输入输出（I / O）和核心电路的公共端之间的静电放电（ESD）保护装置包括第一和第二合并双极晶体管。 第一晶体管的基极用作第二晶体管的集电极，第二晶体管的基极用作第一晶体管的集电极，基极分别具有第一宽度和第二宽度。 第一电阻耦合在第一晶体管的发射极和基极之间，第二电阻耦合在第二晶体管的发射极和基极之间。 ESD触发电压Vt1和保持电压Vh可以通过选择合适的基极宽度和电阻来独立优化。 通过将Vh增加到大致相等的Vt1，ESD保护更稳健，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压。

公开(公告)号：US20110176243A1

公开(公告)日：2011-07-21

申请号：US12689666

申请日：2010-01-19

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H02H9/04 ,  H01L21/8222

CPC分类号： H01L27/0259

摘要： A stacked electrostatic discharge (ESD) protection clamp (99, 100-104) for protecting associated devices or circuits (24) comprises two or more series coupled (stacked) bipolar transistors (70, 700) whose individual trigger voltages Vt1 depend on their base-collector spacing D. A first (70-1, 700-1) of the transistors (70, 700) has a spacing DZ1 chosen within a D range Z1 whose slope (ΔVt1/ΔD) has a first value (ΔVt1/ΔD)Z1, and a second (70-2, 700-2) of the transistors (70, 700) has a spacing value D(Z2 or Z3) chosen within a D range Z2 or Z3 whose slope (ΔVt1/ΔD) has a second value (ΔVt1/ΔD)(Z2 or Z3) less than the first value (ΔVt1/ΔD)Z1. The sensitivity of the ESD stack trigger voltage Vt1STACK to base-collector spacing variations ΔD during manufacture is much reduced, for example, by as much as 50% for a 2-stack and more for 3-stacks and beyond. A wide range of Vt1STACK values can be obtained that are less sensitive to unavoidable manufacturing spacing variations ΔD.

摘要翻译： 用于保护相关器件或电路（24）的叠层静电放电（ESD）保护钳（99,100-104）包括两个或多个串联耦合（堆叠）双极晶体管（70,700），其各自的触发电压Vt1取决于它们的基极 - 收集器间隔D.晶体管（70,700）的第一（70-1,700-1）具有在D范围Z1内选择的间隔DZ1，其中斜率（＆Dgr; Vt1 /＆Dgr; D）具有第一值 晶体管（70,700）的第二（70-2,700-2）具有在D范围Z2或Z3内选择的间隔值D（Z2或Z3），其斜率 （＆Dgr; Vt1 /＆Dgr; D）具有小于第一值（＆Dgr; Vt1 /＆Dgr; D）Z1的第二值（＆Dgr; Vt1 /＆Dgr; D）（Z2或Z3）。 ESD堆栈触发电压Vt1STACK对制造过程中基极集电极间距变化和Dgr D的灵敏度大大降低，例如，2堆叠多达50％，3堆叠以上更多。 可以获得对不可避免的制造间距变化敏感的大范围的Vt1STACK值。

公开(公告)号：US09018072B2

公开(公告)日：2015-04-28

申请号：US14168813

申请日：2014-01-30

申请人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

发明人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L27/02 ,  H01L29/735 ,  H01L29/08

CPC分类号： H01L29/66234 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（＆Dgr; Vt1）MAX的最大值（例如，由半导体晶粒或晶片上的晶体管（21,21'，70,700）的不同方位取向） 大大减少。 触发电压一致性和制造产量提高。

公开(公告)号：US20110176244A1

公开(公告)日：2011-07-21

申请号：US12690771

申请日：2010-01-20

申请人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

发明人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

IPC分类号： H02H9/04 ,  H01L21/331 ,  H01L29/73

CPC分类号： H01L29/66234 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（＆Dgr; Vt1）MAX的最大值（例如，由半导体晶粒或晶片上的晶体管（21,21'，70,700）的不同方位取向） 大大减少。 触发电压一致性和制造产量提高。

公开(公告)号：US08648419B2

公开(公告)日：2014-02-11

申请号：US12690771

申请日：2010-01-20

申请人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

发明人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

IPC分类号： H01L21/331 ,  H01L23/62

CPC分类号： H01L29/66234 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（DeltaVt1）MAX，例如由于半导体晶片或晶片上的晶体管（21,21'，70,700）的不同方位取向是多少 减少 触发电压一致性和制造产量提高。

公开(公告)号：US08928084B2

公开(公告)日：2015-01-06

申请号：US12598282

申请日：2007-05-04

申请人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron ,  Nicolas Nolhier

发明人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron ,  Nicolas Nolhier

IPC分类号： H01L23/60 ,  H01L29/08 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/78

CPC分类号： H01L29/0821 ,  H01L27/0259 ,  H01L29/0619 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.

摘要翻译： 被布置为在用于提供ESD保护的触发电压（Vt1）下有效的ESD保护器件包括形成在第一导电类型的半导体层中的第一导电类型的第一区域，第一区域从表面 并且耦合到所述半导体器件的第一电流电极（C），形成在从所述半导体层的表面延伸的所述半导体层中的第二导电类型的阱区域和所述第二导电性的第二区域 形成在所述阱区中，所述第二区耦合到第二电流电极（B）。 ESD保护装置还包括形成在第一电流电极（C）和阱区域之间的半导体层中并且从半导体层的表面延伸预定深度的第二导电类型的浮动区域。 浮动区域与阱区分离预定距离，其值被选择为使得当ESD保护器件处于活动状态时，浮动区域位于阱区域和半导体层之间的PN结的耗尽区域内 。 浮动区域具有选择的掺杂浓度，使得当ESD保护器件有效并且选择预定深度使得浮动区域修改PN结附近的空间电荷区域时，浮动区域未完全耗尽。 还公开了根据第二实施例的ESD保护装置。

公开(公告)号：US08022505B2

公开(公告)日：2011-09-20

申请号：US12282486

申请日：2006-03-13

申请人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron

发明人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron

IPC分类号： H01L27/082 ,  H01L23/62 ,  H01L29/76 ,  H01L31/062 ,  H01L29/94

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.

摘要翻译： 半导体器件结构包括多个垂直层和多个导电元件，其中垂直层和多个导电元件协同工作以起到至少两个并联的有源器件的作用。 半导体器件结构还可以包括多个水平导电元件，其中该结构被布置成支撑至少两个并流电流，使得第一电流流过多个垂直导电元件，并且第二电流跨越多个 的水平导电元件。