摘要:
An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.
摘要:
An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.
摘要:
A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.
摘要:
A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.
摘要:
An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.
摘要:
A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.
摘要:
Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1
摘要:
An electrostatic discharge (ESD) protection device (11, 60, 80) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24), comprises, first (70, 90) and second (72, 92) merged bipolar transistors (70, 90; 72, 92). A base (62, 82) of the first (70, 90) transistor serves as collector of the second transistor (72, 92) and the base of the second transistor (72, 92) serves as collector of the first (70, 90) transistor, the bases (62, 82) having, respectively, first width (74, 94) and second width (76, 96). A first resistance (78, 98) is coupled between an emitter (67, 87) and base (62, 82) of the first transistor (70, 90) and a second resistance (79, 99) is coupled between an emitter (68, 88) and base (64, 42) of the second transistor (92, 92). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths (74, 94; 76, 96) and resistances (78, 98; 79, 99). By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage).
摘要:
An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.
摘要:
An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.