公开(公告)号：US08928084B2

公开(公告)日：2015-01-06

申请号：US12598282

申请日：2007-05-04

申请人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron ,  Nicolas Nolhier

发明人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron ,  Nicolas Nolhier

IPC分类号： H01L23/60 ,  H01L29/08 ,  H01L27/02 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L29/735 ,  H01L29/78

CPC分类号： H01L29/0821 ,  H01L27/0259 ,  H01L29/0619 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.

摘要翻译： 被布置为在用于提供ESD保护的触发电压（Vt1）下有效的ESD保护器件包括形成在第一导电类型的半导体层中的第一导电类型的第一区域，第一区域从表面 并且耦合到所述半导体器件的第一电流电极（C），形成在从所述半导体层的表面延伸的所述半导体层中的第二导电类型的阱区域和所述第二导电性的第二区域 形成在所述阱区中，所述第二区耦合到第二电流电极（B）。 ESD保护装置还包括形成在第一电流电极（C）和阱区域之间的半导体层中并且从半导体层的表面延伸预定深度的第二导电类型的浮动区域。 浮动区域与阱区分离预定距离，其值被选择为使得当ESD保护器件处于活动状态时，浮动区域位于阱区域和半导体层之间的PN结的耗尽区域内 。 浮动区域具有选择的掺杂浓度，使得当ESD保护器件有效并且选择预定深度使得浮动区域修改PN结附近的空间电荷区域时，浮动区域未完全耗尽。 还公开了根据第二实施例的ESD保护装置。

公开(公告)号：US08022505B2

公开(公告)日：2011-09-20

申请号：US12282486

申请日：2006-03-13

申请人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron

发明人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron

IPC分类号： H01L27/082 ,  H01L23/62 ,  H01L29/76 ,  H01L31/062 ,  H01L29/94

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.

摘要翻译： 半导体器件结构包括多个垂直层和多个导电元件，其中垂直层和多个导电元件协同工作以起到至少两个并联的有源器件的作用。 半导体器件结构还可以包括多个水平导电元件，其中该结构被布置成支撑至少两个并流电流，使得第一电流流过多个垂直导电元件，并且第二电流跨越多个 的水平导电元件。

公开(公告)号：US20100127305A1

公开(公告)日：2010-05-27

申请号：US12598282

申请日：2007-05-04

申请人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron ,  Nicolas Nolhier

发明人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron ,  Nicolas Nolhier

IPC分类号： H01L23/60 ,  H01L29/08 ,  H01L29/06

CPC分类号： H01L29/0821 ,  H01L27/0259 ,  H01L29/0619 ,  H01L29/1008 ,  H01L29/6625 ,  H01L29/66681 ,  H01L29/735 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： An ESD protection device, which is arranged to be active at a triggering voltage (Vt1) for providing ESD protection, comprises a first region of the first conductivity type formed in a semiconductor layer of the first conductivity type, the first region extending from a surface of the semiconductor layer and being coupled to a first current electrode (C) of the semiconductor device, a well region of a second conductivity type formed in the semiconductor layer extending from the surface of the semiconductor layer, and a second region of the second conductivity type formed in the well region, the second region being coupled to a second current electrode (B). The ESD protection device further comprises a floating region of the second conductivity type formed in the semiconductor layer between the first current electrode (C) and the well region and extending from the surface of the semiconductor layer a predetermined depth. The floating region is separated from the well region by a predetermined distance, a value of which is selected such that the floating region is located within a depletion region of a PN junction between the well region and the semiconductor layer when the ESD protection device is active. The floating region has a doping concentration selected such that the floating region is not fully depleted when the ESD protection device is active and the predetermined depth is selected such that the floating region modifies a space charge region near the PN junction. An ESD protection device according to a second embodiment is also disclosed.

摘要翻译： 被布置为在用于提供ESD保护的触发电压（Vt1）下有效的ESD保护器件包括形成在第一导电类型的半导体层中的第一导电类型的第一区域，第一区域从表面 并且耦合到所述半导体器件的第一电流电极（C），形成在从所述半导体层的表面延伸的所述半导体层中的第二导电类型的阱区域和所述第二导电性的第二区域 形成在所述阱区中，所述第二区耦合到第二电流电极（B）。 ESD保护装置还包括形成在第一电流电极（C）和阱区域之间的半导体层中并且从半导体层的表面延伸预定深度的第二导电类型的浮动区域。 浮动区域与阱区分离预定距离，其值被选择为使得当ESD保护器件处于活动状态时，浮动区域位于阱区域和半导体层之间的PN结的耗尽区域内 。 浮动区域具有选择的掺杂浓度，使得当ESD保护器件有效并且选择预定深度使得浮动区域修改PN结附近的空间电荷区域时，浮动区域未完全耗尽。 还公开了根据第二实施例的ESD保护装置。

公开(公告)号：US20090057833A1

公开(公告)日：2009-03-05

申请号：US12282486

申请日：2006-03-13

申请人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron

发明人： Philippe Renaud ,  Patrice Besse ,  Amaury Gendron

IPC分类号： H01L27/06

CPC分类号： H01L27/0259 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device structure comprises a plurality of vertical layers and a plurality of conductive elements wherein the vertical layers and plurality of conductive elements co-operate to function as at least two active devices in parallel. The semiconductor device structure may also comprise a plurality of horizontal conductive elements wherein the structure is arranged to support at least two concurrent current flows, such that a first current flow is across the plurality of vertical conductive elements and a second current flow is across the plurality of horizontal conductive elements.

摘要翻译： 半导体器件结构包括多个垂直层和多个导电元件，其中垂直层和多个导电元件协同工作以起到至少两个并联的有源器件的作用。 半导体器件结构还可以包括多个水平导电元件，其中该结构被布置成支撑至少两个并流电流，使得第一电流流过多个垂直导电元件，并且第二电流跨越多个 的水平导电元件。

公开(公告)号：US20120119331A1

公开(公告)日：2012-05-17

申请号：US12944931

申请日：2010-11-12

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H01L29/72 ,  H01L21/331

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.

摘要翻译： 提供一种区域高效，高电压，单极性的ESD保护装置（300），其包括p型衬底（303）; 第一p阱（308-1），其形成在所述衬底中并且尺寸设置成包含连接到阴极端子的n +和p +接触区域（310,312）; 形成在所述基板中并且尺寸仅包含连接到阳极端子的p +接触区域（311）的第二独立p阱（308-2） 以及形成在基板中以围绕和分离第一和第二半导体区域的电浮置n型隔离结构（304,306,307-2）。 当超过触发电压电平的正电压被施加到阴极和阳极端子时，ESD保护装置将固有的可控硅触发到快速恢复模式，以提供通过用于放电ESD电流的结构的低阻抗路径。

公开(公告)号：US20110175198A1

公开(公告)日：2011-07-21

申请号：US12956686

申请日：2010-11-30

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L29/73 ,  H01L21/331

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： A stackable electrostatic discharge (ESD) protection clamp (21) for protecting a circuit core (24) comprises, a bipolar transistor (56, 58) having a base region (74, 51, 52, 85) with a base contact (77) therein and an emitter (78) spaced a lateral distance Lbe from the base contact (77), and a collector (80, 86, 762) proximate the base region (74, 51, 52, 85). The base region (74, 51, 52, 85) comprises a first portion (51) including the base contact (77) and emitter (78), and a second portion (52) with a lateral boundary (752) separated from the collector (86, 762) by a breakdown region (84) whose width D controls the clamp trigger voltage, the second portion (52) lying between the first portion (51) and the boundary (752). The damage-onset threshold current It2 of the ESD clamp (21) is improved by increasing the parasitic resistance Rbe of the emitter-base region (74, 51, 52, 85), by for example, increasing Lbe or decreasing the relative doping density of the first portion (51) or a combination thereof.

摘要翻译： 用于保护电路芯（24）的可堆叠静电放电（ESD）保护夹具（21）包括：具有基部接触（77）的基极区域（74,51,52,85）的双极晶体管（56,58） 以及与基部触点（77）间隔开横向距离Lbe的发射器（78）和靠近基部区域（74,51,52,85）的收集器（80,86,762）。 基部区域（74,51,52,85）包括包括基部触头（77）和发射极（78）的第一部分（51）和具有与集电器分离的侧边界（752）的第二部分（52） （86,762）由其宽度D控制钳位触发电压的击穿区域（84），第二部分（52）位于第一部分（51）和边界（752）之间。 通过增加发射极 - 基极区（74,51,52,85）的寄生电阻Rbe，例如增加Lbe或减小相对掺杂密度来改善ESD钳位（21）的损伤起始阈值电流It2 的第一部分（51）或其组合。

公开(公告)号：US08647955B2

公开(公告)日：2014-02-11

申请号：US13770548

申请日：2013-02-19

申请人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

发明人： Rouying Zhan ,  Amaury Gendron ,  Chai Ean Gill

IPC分类号： H01L21/8222 ,  H01L23/62

CPC分类号： H01L21/8228 ,  H01L27/0259 ,  H01L29/66234

摘要： Methods for forming an electrostatic discharge protection (ESD) clamps are provided. In one embodiment, the method includes forming at least one transistor having a first well region of a first conductivity type extending into a substrate. At least one transistor is formed having another well region of a second opposite conductivity type, which extends into the substrate to partially form a collector. The lateral edges of the transistor well regions are separated by a distance D, which at least partially determines a threshold voltage Vt1 of the ESD clamp. A base contact of the first conductivity type is formed in the first well region and separated from an emitter of the second conductivity type by a lateral distance Lbe. The first doping density and the lateral distance Lbe are selected to provide a parasitic base-emitter resistance Rbe in the range of 1

摘要翻译： 提供了形成静电放电保护（ESD）夹具的方法。 在一个实施例中，该方法包括形成至少一个具有延伸到衬底中的第一导电类型的第一阱区的晶体管。 至少一个晶体管形成有具有第二相反导电类型的另一阱区，其延伸到衬底中以部分地形成集电极。 晶体管阱区的横向边缘被隔开距离D，距离D至少部分地确定ESD钳位的阈值电压Vt1。 第一导电类型的基极接触形成在第一阱区中，并且与第二导电类型的发射极分开横向距离Lbe。 选择第一掺杂浓度和横向距离Lbe以在1

公开(公告)号：US20100320501A1

公开(公告)日：2010-12-23

申请号：US12487031

申请日：2009-06-18

申请人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Rouying Zhan

IPC分类号： H01L29/73 ,  H01L21/33

CPC分类号： H01L21/00 ,  H01L27/0259 ,  H01L27/0262 ,  H01L29/0649 ,  H01L29/66121 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection device (11, 60, 80) coupled across input-output (I/O) (22) and common (23) terminals of a core circuit (24), comprises, first (70, 90) and second (72, 92) merged bipolar transistors (70, 90; 72, 92). A base (62, 82) of the first (70, 90) transistor serves as collector of the second transistor (72, 92) and the base of the second transistor (72, 92) serves as collector of the first (70, 90) transistor, the bases (62, 82) having, respectively, first width (74, 94) and second width (76, 96). A first resistance (78, 98) is coupled between an emitter (67, 87) and base (62, 82) of the first transistor (70, 90) and a second resistance (79, 99) is coupled between an emitter (68, 88) and base (64, 42) of the second transistor (92, 92). ESD trigger voltage Vt1 and holding voltage Vh can be independently optimized by choosing appropriate base widths (74, 94; 76, 96) and resistances (78, 98; 79, 99). By increasing Vh to approximately equal Vt1, the ESD protection is more robust, especially for applications with narrow design windows, for example, with operating voltage close to the degradation voltage).

摘要翻译： 耦合在核心电路（24）的输入输出（I / O）（22）和公共（23）端子之间的静电放电（ESD）保护装置（11,60,80）包括：第一（70,90） 和第二（72,92）合并的双极晶体管（70,90; 72,92）。 第一（70,90）晶体管的基极（62,82）用作第二晶体管（72,92）的集电极，第二晶体管（72,92）的基极用作第一晶体管（70,90）的集电极 ）晶体管，所述基座（62,82）分别具有第一宽度（74,94）和第二宽度（76,96）。 第一电阻（78,98）耦合在第一晶体管（70,90）的发射极（67,87）和基极（62,82）之间，第二电阻（79,99）耦合在发射极（68,98） ，88）和第二晶体管（92,92）的基极（64,42）。 可以通过选择合适的基准宽度（74,94,76,96）和电阻（78,98,79,99）来独立地优化ESD触发电压Vt1和保持电压Vh。 通过将Vh增加到大致相等的Vt1，ESD保护更加坚固，特别是对于具有窄设计窗口的应用，例如，工作电压接近劣化电压）。

公开(公告)号：US09018072B2

公开(公告)日：2015-04-28

申请号：US14168813

申请日：2014-01-30

申请人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

发明人： Amaury Gendron ,  Chai Ean Gill ,  Changsoo Hong

IPC分类号： H01L21/331 ,  H01L29/66 ,  H01L27/02 ,  H01L29/735 ,  H01L29/08

CPC分类号： H01L29/66234 ,  H01L27/0259 ,  H01L29/0821 ,  H01L29/6625 ,  H01L29/735

摘要： An electrostatic discharge (ESD) protection clamp (21, 21′, 70, 700) for protecting associated devices or circuits (24), comprises a bipolar transistors (21, 21′, 70, 700) in which doping of facing base (75) and collector (86) regions is arranged so that avalanche breakdown occurs preferentially within a portion (84, 85) of the base region (74, 75) of the device (70, 700) away from the overlying dielectric-semiconductor interface (791). Maximum variations (ΔVt1)MAX of ESD triggering voltage Vt1 as a function of base-collector spacing dimensions D due, for example, to different azimuthal orientations of transistors (21, 21′, 70, 700) on a semiconductor die or wafer is much reduced. Triggering voltage consistency and manufacturing yield are improved.

摘要翻译： 一种用于保护相关器件或电路（24）的静电放电（ESD）保护钳（21,21'，70,700），包括双极晶体管（21,21'，70,700），其中面向基底（75 ）和集电极（86）区域布置成使得雪崩击穿优先地位于远离上覆电介质 - 半导体界面（791）的器件（70,700）的基极区域（74,75）的部分（84,85）内 ）。 作为基极 - 集电极间距尺寸D的函数的ESD触发电压Vt1的最大变化（＆Dgr; Vt1）MAX的最大值（例如，由半导体晶粒或晶片上的晶体管（21,21'，70,700）的不同方位取向） 大大减少。 触发电压一致性和制造产量提高。

公开(公告)号：US08390092B2

公开(公告)日：2013-03-05

申请号：US12944931

申请日：2010-11-12

申请人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

发明人： Amaury Gendron ,  Chai Ean Gill ,  Vadim A. Kushner ,  Rouying Zhan

IPC分类号： H01L23/58

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An area-efficient, high voltage, single polarity ESD protection device (300) is provided which includes an p-type substrate (303); a first p-well (308-1) formed in the substrate and sized to contain n+ and p+ contact regions (310, 312) that are connected to a cathode terminal; a second, separate p-well (308-2) formed in the substrate and sized to contain only a p+ contact region (311) that is connected to an anode terminal; and an electrically floating n-type isolation structure (304, 306, 307-2) formed in the substrate to surround and separate the first and second semiconductor regions. When a positive voltage exceeding a triggering voltage level is applied to the cathode and anode terminals, the ESD protection device triggers an inherent thyristor into a snap-back mode to provide a low impedance path through the structure for discharging the ESD current.