公开(公告)号：US10423438B2

公开(公告)日：2019-09-24

申请号：US15282282

申请日：2016-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Mark Bradley Davis ,  Robert Michael Johnson ,  Christopher Joseph Pettey ,  Asif Khan ,  Nafea Bshara

IPC: G06F9/455 ,  G06F9/50 ,  G06F15/76

Abstract: In a multi-tenant environment, separate virtual machines can be used for configuring and operating different subsets of programmable integrated circuits, such as a Field Programmable Gate Array (FPGA). The programmable integrated circuits can communicate directly with each other within a subset, but cannot communicate between subsets. Generally, all of the subsets of programmable ICs are within a same host server computer within the multi-tenant environment, and are sandboxed or otherwise isolated from each other so that multiple customers can share the resources of the host server computer without knowledge or interference with other customers.

公开(公告)号：US10353843B1

公开(公告)日：2019-07-16

申请号：US15946683

申请日：2018-04-05

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan ,  Thomas A. Volpe ,  Robert Michael Johnson

IPC: G06F13/40 ,  G06F13/42

Abstract: A device can include one of more configurable packet processing pipelines to process a plurality of packets. Each configurable packet processing pipeline can include a plurality of packet processing components, wherein each packet processing component is configured to perform one or more packet processing operations for the device. The plurality of packet processing components are coupled to a packet processing interconnect, wherein each packet processing component is configured to route the packets through the packet processing interconnect for the one or more configurable packet processing pipelines.

公开(公告)号：US20190213155A1

公开(公告)日：2019-07-11

申请号：US16361007

申请日：2019-03-21

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US10282330B2

公开(公告)日：2019-05-07

申请号：US15280624

申请日：2016-09-29

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Islam Mohamed Hatem Abdulfattah Mohamed Atta ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Christopher Joseph Pettey ,  Nafea Bshara ,  Erez Izenberg

IPC: G06F15/18 ,  G06F13/362 ,  G06F13/40 ,  G06F9/50

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a plurality of reconfigurable logic regions. Each reconfigurable region can include hardware that is configurable to implement an application logic design. The host logic can be used for separately encapsulating each of the reconfigurable logic regions. The host logic can include a plurality of data path functions where each data path function can include a layer for formatting data transfers between a host interface and the application logic of a corresponding reconfigurable logic region. The host interface can be configured to apportion bandwidth of the data transfers generated by the application logic of the respective reconfigurable logic regions.

公开(公告)号：US20180089132A1

公开(公告)日：2018-03-29

申请号：US15279232

申请日：2016-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F9/44505 ,  G06F13/4282 ,  G06F15/7867 ,  G06F15/7871

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US20180088992A1

公开(公告)日：2018-03-29

申请号：US15279164

申请日：2016-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan ,  Christopher Joseph Pettey ,  Erez Izenberg ,  Nafea Bshara

IPC: G06F9/50 ,  G06F13/40

CPC classification number: G06F9/5005 ,  G06F9/45558 ,  G06F9/5077 ,  G06F9/541 ,  G06F13/4068 ,  G06F2213/0038

Abstract: A multi-tenant environment is described with configurable hardware logic (e.g., a Field Programmable Gate Array (FPGA)) positioned on a host server computer. For communicating with the configurable hardware logic, an intermediate host integrated circuit (IC) is positioned between the configurable hardware logic and virtual machines executing on the host server computer. The host IC can include management functionality and mapping functionality to map requests between the configurable hardware logic and the virtual machines. Shared peripherals can be located either on the host IC or the configurable hardware logic. The host IC can apportion resources amongst the different configurable hardware logics to ensure that no one customer can over consume resources.

公开(公告)号：US09886410B1

公开(公告)日：2018-02-06

申请号：US14614360

申请日：2015-02-04

Applicant: Amazon Technologies, Inc.

Inventor： Mark Bradley Davis ,  Asif Khan

IPC: G06F13/20 ,  G06F13/42 ,  G06F13/16 ,  G06F13/38

CPC classification number: G06F13/4221 ,  G06F13/1663 ,  G06F13/385

Abstract: An electronics adapter and method are disclosed herein. The electronics adapter can include a plurality of interface ports, with each interface port from the device coupled to a processor from a plurality of processors, and a controller communicatively coupled to the interface ports. The controller may be configured to determine a function or transaction attributes, which are serviced by instructions executed by one of the processors. The controller may be further configured to determine at least one interface port on the adapter to transmit the transaction based on the function or the attributes using an updatable mapping between the function or the attributes and the interface port, and transmit a request for the transaction using the interface port for processing of the transaction by the processor coupled to the interface port.

公开(公告)号：US09864701B1

公开(公告)日：2018-01-09

申请号：US14643932

申请日：2015-03-10

Applicant: Amazon Technologies, Inc.

Inventor： Asif Khan ,  Rahul Gautam Patel ,  Mark Bradley Davis

IPC: G06F12/1081 ,  G06F12/06 ,  G06F13/10

CPC classification number: G06F12/1081 ,  G06F12/0653 ,  G06F13/102 ,  G06F2212/1041 ,  G06F2212/154 ,  G06F2212/657

Abstract: One or more resources for an SoC can be directly mapped to a host address space in a host system as peripheral bus functions. A translation unit can provide translation between the host address space and an SoC address space for transactions targeted for a resource from the one or more resources to facilitate performing the transactions with the resource using the host address space. Some embodiments of the technology can provide peer to peer capability for communication between the SoC resources using the translation unit.

公开(公告)号：US12204481B2

公开(公告)日：2025-01-21

申请号：US18383833

申请日：2023-10-25

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

公开(公告)号：US20240232117A9

公开(公告)日：2024-07-11

申请号：US18383833

申请日：2023-10-25

Applicant: Amazon Technologies, Inc.

Inventor： Islam Atta ,  Christopher Joseph Pettey ,  Asif Khan ,  Robert Michael Johnson ,  Mark Bradley Davis ,  Erez Izenberg ,  Nafea Bshara ,  Kypros Constantinides

IPC: G06F13/40 ,  G06F9/445 ,  G06F13/42 ,  G06F15/78

CPC classification number: G06F13/4068 ,  G06F9/44505 ,  G06F13/4282 ,  G06F15/7867 ,  G06F15/7871

Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.