公开(公告)号：US11004849B2

公开(公告)日：2021-05-11

申请号：US16294431

申请日：2019-03-06

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01C7/12 ,  H01L27/02 ,  H01L29/87

Abstract: Electrical overstress protection for high speed applications, such as integrated multiple subsystem communications, is provided. In certain embodiments, a semiconductor die with distributed and configurable electrical overstress protection is provided. The semiconductor die includes signal pads, a core circuit electrically connected to the signal pads, and a configurable overstress protection array operable to protect the core circuit from electrical overstress at the signal pads. The configurable overstress protection array includes a plurality of segmented overstress protection devices of two or more different device types, and both a number of selected overstress protection devices and a device type of the selected overstress protection devices is programmable. The subsystems configurations are enabled in FinFET technology. Such configurable overstress protection arrays can be distributed across the die to protect not only core circuit sub-systems at the die pads, but also between internal sub-system communication interfaces operating in different power domains.

公开(公告)号：US12261593B2

公开(公告)日：2025-03-25

申请号：US18157550

申请日：2023-01-20

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Jonathan G. Pfeifer

IPC: H03K17/081 ,  H01L27/02 ,  H01L29/74 ,  H01L29/78

Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.

公开(公告)号：US20210257364A1

公开(公告)日：2021-08-19

申请号：US17306563

申请日：2021-05-03

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Andrew Lewine

IPC: H01L27/092 ,  H01L29/87 ,  H01L27/02 ,  H01C7/12

Abstract: Electrical overstress protection for high speed applications is provided. In certain embodiments, a method of distributed and customizable electrical overstress protection for a semiconductor die is provided. The method includes configuring a heterogeneous overstress protection array that includes a customizable forward protection circuit electrically connected between a power high pad, a power low pad, and a signal pad and distributed across the semiconductor die, including selecting a number of segmented overstress protection devices from a plurality of available overstress protection devices of the customizable protection circuit. The method also includes choosing a device type of the selected segmented overstress protection devices from amongst two or more different device types providing complementary protection characteristics and protecting a core circuit from electrical overstress using the selected segmented overstress protection devices, the core circuit electrically connected to at least the signal pad, the power high pad, and the power low pad.

公开(公告)号：US20200381417A1

公开(公告)日：2020-12-03

申请号：US16700989

申请日：2019-12-02

Applicant: Analog Devices, Inc.

Inventor： Javier A. Salcedo ,  Linfeng He

IPC: H01L27/02 ,  H02H9/04 ,  H01L29/74 ,  H01L29/08 ,  H01L29/417 ,  H01L29/40

Abstract: A semiconductor die with high-voltage tolerant electrical overstress circuit architecture is disclosed. One embodiment of the semiconductor die includes a signal pad, a ground pad, a core circuit electrically connected to the signal pad, and a stacked thyristor protection device. The stacked thyristor includes a first thyristor and a resistive thyristor electrically connected in a stack between the signal pad and the ground pad, which enhances the holding voltage of the circuit relatively to an implementation with only the thyristor. Further, the resistive thyristor includes a PNP bipolar transistor and a NPN bipolar transistor that are cross-coupled, and an electrical connection between a collector of the PNP bipolar transistor and a collector of the NPN bipolar transistor. This allows the resistive thyristor to exhibit both thyristor characteristics and resistive characteristics based on a level of current flow.

公开(公告)号：US08730630B2

公开(公告)日：2014-05-20

申请号：US13863155

申请日：2013-04-15

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier A. Salcedo

IPC: H02H9/00

CPC classification number: H02H3/22 ,  H01L27/0259 ,  H02H9/046

Abstract: Apparatuses and methods for providing transient electrical event protection are disclosed. In one embodiment, an apparatus comprises a detection and timing circuit, a current amplification circuit, and a clamping circuit. The detection and timing circuit is configured to detect a presence or absence of a transient electrical event at a first node, and to generate a first current for a first duration upon detection of the transient electrical event. The current amplification circuit is configured to receive the first current from the detection and timing circuit and to amplify the first current to generate a second current. The clamping circuit is electrically connected between the first node and a second node and receives the second current for activation. The clamping circuit is configured to activate a low impedance path between the first and second nodes in response to the second current, and to otherwise deactivate the low impedance path.

Abstract translation: 公开了用于提供瞬时电气事件保护的装置和方法。 在一个实施例中，一种装置包括检测和定时电路，电流放大电路和钳位电路。 检测和定时电路被配置为检测在第一节点处的瞬时电事件的存在或不存在，并且在检测到瞬态电事件时产生第一持续时间的第一电流。 电流放大电路被配置为从检测和定时电路接收第一电流并且放大第一电流以产生第二电流。 钳位电路电连接在第一节点和第二节点之间，并接收用于激活的第二电流。 钳位电路被配置为响应于第二电流来激活第一和第二节点之间的低阻抗路径，并且否则去激活低阻抗路径。

公开(公告)号：US20130300487A1

公开(公告)日：2013-11-14

申请号：US13945701

申请日：2013-07-18

Applicant: Analog Devices, Inc.

Inventor： Jeffrey G. Barrow ,  Javier A. Salcedo ,  A. Paul Brokaw

IPC: H01L29/745

CPC classification number: H01L29/745 ,  H01L29/7408 ,  H01L29/7455

Abstract: A semiconductor switch comprises a PNPN structure arranged to provide an SCR-like functionality, and a MOS gate structure, preferably integrated on a common substrate. The switch includes ohmic contacts for the MOS gate, and for the cathode and gate regions of the PNPN structure; the anode contact is intrinsic. A fixed voltage is typically applied to an external node. The MOS gate structure allows current to be conducted between the external node and the intrinsic anode when on, and the PNPN structure conducts the current from the anode to the cathode when an appropriate voltage is applied to the gate contact. Regenerative feedback keeps the switch on once it begins to conduct. The MOS gate inhibits the flow of current between the external node and anode—and thereby turns off the switch—when off. When on, the MOS gate's channel resistance serves as a ballast resistor.

Abstract translation: 半导体开关包括被布置为提供类SCR功能的PNPN结构，以及优选地集成在公共基板上的MOS栅极结构。 该开关包括用于MOS栅极的欧姆接触，以及用于PNPN结构的阴极和栅极区域; 阳极接触是固有的。 固定电压通常被施加到外部节点。 MOS栅极结构允许在导通时在外部节点和本征阳极之间传导电流，并且当适当的电压施加到栅极触点时，PNPN结构将电流从阳极传导到阴极。 再生反馈一旦开始进行就保持开关状态。 MOS门禁止外部节点和阳极之间的电流流动，从而在关闭时关闭开关。 当导通时，MOS栅极的沟道电阻用作镇流电阻。