公开(公告)号：US20240014270A1

公开(公告)日：2024-01-11

申请号：US18370626

申请日：2023-09-20

Applicant: FUJI ELECTRIC CO., LTD.

Inventor： Keiji OKUMURA

IPC: H01L29/10 ,  H01L29/739 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/66 ,  H01L29/16 ,  H01L29/745

CPC classification number: H01L29/1095 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/7806 ,  H01L29/0865 ,  H01L29/7811 ,  H01L29/4236 ,  H01L29/417 ,  H01L29/66068 ,  H01L29/1608 ,  H01L29/745 ,  H01L29/083 ,  H01L29/66348 ,  H01L21/049

Abstract: An insulated-gate semiconductor device, which has trenches arranged in a chip structure, the trenches defining both sidewalls in a first and second sidewall surface facing each other, includes: a first unit cell including a main-electrode region in contact with a first sidewall surface of a first trench, a base region in contact with a bottom surface of the main-electrode region and the first sidewall surface, a drift layer in contact with a bottom surface of the base region and the first sidewall surface, and a gate protection-region in contact with the second sidewall surface and a bottom surface of the first trench; and a second unit cell including an operation suppression region in contact with a first sidewall surface and a second sidewall surface of a second trench, wherein the second unit cell includes the second trench located at one end of an array of the trenches.

公开(公告)号：US09899512B2

公开(公告)日：2018-02-20

申请号：US15052664

申请日：2016-02-24

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Ljubisa Dragoljub Stevanovic ,  Gregory Thomas Dunne ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/417 ,  H01L29/16 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/7395 ,  H01L29/745 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8083

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm−2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

公开(公告)号：US20170243935A1

公开(公告)日：2017-08-24

申请号：US15295779

申请日：2016-10-17

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Ljubisa Dragoljub Stevanovic ,  Peter Almern Losee

IPC: H01L29/06 ,  G06F17/50 ,  H01L23/556 ,  H01L29/16 ,  H01L23/552

CPC classification number: H01L29/06 ,  G06F17/5036 ,  G06F17/5068 ,  G06F2217/06 ,  H01L23/552 ,  H01L23/556 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/745 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8083 ,  H01L29/861 ,  H01L29/8611 ,  H01L29/868 ,  H01L29/872

Abstract: In one embodiment, a method of manufacturing a silicon-carbide (SiC) device includes receiving a selection of a specific terrestrial cosmic ray (TCR) rating at a specific applied voltage, determining a breakdown voltage for the SiC device based at least on the specific TCR rating at the specific applied voltage, determining drift layer design parameters based at least on the breakdown voltage. The drift layer design parameters include doping concentration and thickness of the drift layer. The method also includes fabricating the SiC device having a drift layer with the determined drift layer design parameters. The SiC device has the specific TCR rating at the specific applied voltage.

公开(公告)号：US09343558B1

公开(公告)日：2016-05-17

申请号：US14850951

申请日：2015-09-10

Applicant: GLOBAL UNICHIP CORPORATION ,  TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yu Lin ,  Ming-Dou Ker ,  Wen-Tai Wang

IPC: H01L29/74 ,  H01L29/749 ,  H01L29/744 ,  H01L29/745 ,  H01L27/02

CPC classification number: H01L29/749 ,  H01L27/0262 ,  H01L29/744 ,  H01L29/745 ,  H01L29/7455 ,  H01L29/87 ,  H01L2924/13034

Abstract: A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.

Abstract translation: 可控硅整流器包括衬底，阱，深掺杂区，第一掺杂区，第二掺杂区，第三掺杂区和第四掺杂区。 孔被放置在基底上并在细胞区域下方。 深掺杂区域设置在阱中。 第一掺杂区具有第一导电类型，并且设置在阱中。 第二掺杂区域和第三掺杂区域具有第一导电类型并且设置在深掺杂区域上。 第四掺杂区域具有第二导电类型，并且设置在第二掺杂区域和第三掺杂区域之间。 第四掺杂区域设置在深掺杂区域上，并且通过深掺杂区域，第二掺杂区域和第三掺杂区域与阱电隔离。

公开(公告)号：US20150349187A1

公开(公告)日：2015-12-03

申请号：US14287388

申请日：2014-05-27

Applicant: Opel Solar, Inc. ,  The University of Connecticut

Inventor： Geoff W. Taylor

IPC: H01L31/113 ,  H01L31/0232 ,  H01L27/144 ,  G02B6/12 ,  H01L31/0352 ,  G02B6/35 ,  G02B6/42 ,  G02B6/43 ,  H01L31/0224 ,  H01L31/0304

CPC classification number: H01L31/1136 ,  G02B6/00 ,  G02B6/12 ,  G02B6/29338 ,  G02B6/3596 ,  G02B6/4295 ,  G02B6/43 ,  G02B2006/12145 ,  H01L27/1443 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/122 ,  H01L29/7392 ,  H01L29/74 ,  H01L29/7424 ,  H01L29/745 ,  H01L29/749 ,  H01L31/022408 ,  H01L31/02327 ,  H01L31/03044 ,  H01L31/03046 ,  H01L31/035209

Abstract: A semiconductor device suitable for power applications includes a thyristor epitaxial layer structure defining an anode region offset vertically from a cathode region with a plurality of intermediate regions therebetween. An anode electrode is electrically coupled to the anode region. A cathode electrode is electrically coupled to the cathode region. A switchable current path that extends vertically between the anode region and the cathode region has a conducting state and a non-conducting state. An epitaxial resistive region is electrically coupled to and extends laterally from one of the plurality of intermediate regions. An FET is provided having a channel that is electrically coupled to the epitaxial resistive region. The FET can be configured to inject (or remove) electrical carriers into (or from) the one intermediate region via the epitaxial resistive region in order to switch the switchable current path between its non-conducting state and its conducting state.

Abstract translation: 适用于功率应用的半导体器件包括限定从阴极区垂直偏移的阳极区的晶闸管外延层结构，其间具有多个中间区。 阳极电极电耦合到阳极区域。 阴极电连接到阴极区。 在阳极区域和阴极区域之间垂直延伸的可切换电流路径具有导通状态和非导通状态。 外延电阻区域电耦合到多个中间区域中的一个并且从其横向延伸。 提供具有电耦合到外延电阻区的沟道的FET。 FET可以被配置为通过外延电阻区域将（或从）一个中间区域注入（或去除）电载体，以便在其导通状态和其导通状态之间切换可切换电流路径。

公开(公告)号：US20080070350A1

公开(公告)日：2008-03-20

申请号：US11873966

申请日：2007-10-17

Applicant: Florin UDREA

Inventor： Florin UDREA

IPC: H01L21/331

CPC classification number: H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one. example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个。 例如，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US07301220B2

公开(公告)日：2007-11-27

申请号：US11133445

申请日：2005-05-20

Applicant: Florin Udrea

Inventor： Florin Udrea

IPC: H01L29/00

CPC classification number: H01L29/7394 ,  H01L29/0839 ,  H01L29/7432 ,  H01L29/745 ,  H01L29/861 ,  H01L29/872

Abstract: A bipolar high voltage/power semiconductor device has a low voltage terminal and a high voltage terminal. The device has a drift region of a first conductivity type and having first and second ends. In one example, a region of the second conductivity type is provided at the second end of the drift region connected directly to the high voltage terminal. In another example, a buffer region of the first conductivity type is provided at the second end of the drift region and a region of a second conductivity type is provided on the other side of the buffer region and connected to the high voltage terminal. Plural electrically floating island regions are provided within the drift region at or towards the second end of the drift region, the plural electrically floating island regions being of the first conductivity type and being more highly doped than the drift region.

Abstract translation: 双极高压/功率半导体器件具有低电压端子和高压端子。 该器件具有第一导电类型的漂移区，并具有第一和第二端。 在一个示例中，第二导电类型的区域设置在直接连接到高电压端子的漂移区域的第二端。 在另一示例中，第一导电类型的缓冲区设置在漂移区的第二端，并且第二导电类型的区域设置在缓冲区的另一侧并连接到高压端。 在漂移区域内或漂移区域的第二端处设置多个电浮岛区域，多个电浮岛区域是第一导电类型并且比漂移区域更加掺杂。

公开(公告)号：US20030122149A1

公开(公告)日：2003-07-03

申请号：US10372402

申请日：2003-02-25

Inventor： Junichi Sakano ,  Hideo Kobayashi ,  Mutsuhiro Mori

IPC: H01L029/74

CPC classification number: H01L29/749 ,  H01L29/7404 ,  H01L29/745 ,  H01L29/7455

Abstract: An MIS gate type semiconductor device having a low resistive loss in the ON state and a wide safe operation region is disclosed. In this semiconductor device, the p-base layer of the thyristor and the emitter electrode are connected together using a suitable nonlinear device. As a result, lower loss and higher capacity of the semiconductor device can be realized in order not only to make it easy to turn ON the thyristor but also to make the safe operation region wide.

Abstract translation: 公开了一种在导通状态下具有低电阻损耗和宽安全操作区域的MIS栅极型半导体器件。 在该半导体器件中，晶闸管的p基极层和发射极电极使用合适的非线性器件连接在一起。 结果，可以实现半导体器件的更低的损耗和更高的容量，以便不仅能够容易地导通晶闸管，而且使安全操作区域变宽。

公开(公告)号：US06423986B1

公开(公告)日：2002-07-23

申请号：US09719327

申请日：2000-12-08

Applicant: Jian J. Zhao

Inventor： Jian J. Zhao

IPC: H01L2987

CPC classification number: H01L29/1602 ,  H01L29/16 ,  H01L29/1608 ,  H01L29/7391 ,  H01L29/7392 ,  H01L29/745

Abstract: Power semiconductor devices have a plurality of semiconductor layers of alternating p-type and n-type conductivity and top and bottom device surfaces. The top semiconductor layer forms a control layer (60). A semiconductor layer junction, remote from both device surfaces, forms a blocking p-n junction (54) capable of sustaining the applied device voltage. A top ohmic contact overlays a top conductive region (64) extending from the top surface into the control layer (60). A conductive tub region (62), spaced apart from the top conductive region (64), extends from the top surface at least through the control layer (60). A field effect region (80) is disposed in the control layer (60) between the top conductive region (64) and tub region (62). A gate contact (18) is formed over the field effect region (80) causing the creation and interruption of a conductive channel (82) between the top conductive region (64) and conductive tub region (62) so as to turn the device on and off.

Abstract translation: 功率半导体器件具有交替的p型和n型导电性以及顶部和底部器件表面的多个半导体层。 顶部半导体层形成控制层（60）。 远离两个器件表面的半导体层结形成能够维持施加的器件电压的阻挡p-n结（54）。 顶部欧姆接触覆盖从顶表面延伸到控制层（60）中的顶部导电区域（64）。 与顶部导电区域（64）间隔开的导电槽区域（62）至少通过控制层（60）从顶表面延伸。 场效应区域（80）设置在顶部导电区域（64）和桶区域（62）之间的控制层（60）中。 在场效应区域（80）上形成栅极接触（18），导致在顶部导电区域（64）和导电槽区域（62）之间的导电通道（82）的产生和中断，以使设备转动 关闭

公开(公告)号：US4963950A

公开(公告)日：1990-10-16

申请号：US188887

申请日：1988-05-02

Applicant: Hsueh-Rong Chang ,  Bantval J. Baliga

Inventor： Hsueh-Rong Chang ,  Bantval J. Baliga

IPC: H01L29/745 ,  H01L29/749

CPC classification number: H01L29/745 ,  H01L29/749

Abstract: A depletion mode thyristor includes a plurality of regenerative segments and a plurality of non-regenerative segments, each of which is elongated in a first direction. Regenerative and non-regenerative segments are interleaved in a second direction perpendicular to said first direction. A plurality of regenerative segments may be disposed between adjacent non-regenerative segments. Adjacent regenerative or non-regenerative segments are spaced apart by gate electrode segments which are effective, upon application of an appropriate bias voltage, for pinching off the regenerative segments to force the current therein to transfer to the non-regenerative segments to turn the device off. This structure enables large quantities of current to be transferred from regenerative segments to non-regenerative segments during turn-off without inducing detrimental current crowding.

Abstract translation: 耗尽型晶闸管包括多个再生段和多个非再生段，每个段在第一方向上是细长的。 再生和非再生段在垂直于所述第一方向的第二方向交错。 多个再生段可以设置在相邻的非再生段之间。 相邻的再生或非再生段由栅极电极段间隔开，栅极电极段在施加适当的偏置电压时有效地夹紧再生段以迫使其中的电流转移到非再生段以将器件关断 。 这种结构使得大量的电流在关断期间不会引起有害的电流拥挤而从再生段传递到非再生段。