公开(公告)号：US5452241A

公开(公告)日：1995-09-19

申请号：US209589

申请日：1994-03-14

Applicant: Bernard Desrosiers ,  Louis Didier ,  Didier Pinchon ,  Andre Steimle

Inventor： Bernard Desrosiers ,  Louis Didier ,  Didier Pinchon ,  Andre Steimle

IPC: G06F7/38 ,  G06F7/483 ,  G06F7/487 ,  G06F7/52 ,  G06F7/527 ,  G06F7/533 ,  G06F7/548 ,  G06F17/10 ,  G06F7/00

CPC classification number: G06F7/4876 ,  G06F7/548 ,  G06F7/49942

Abstract: A method for approximating mathematical functions using polynomial expansions is implemented in a numeric processing system. A partial remainder operation is set forth for high accuracy reduction of polynomials whose arguments are greater than pi/4. The method may be practiced in a processor having a bus of approximately half the width of the precision of the desired result. Temporary registers are utilized for the storage of intermediate results. Full bus width accuracy is obtained through successive half bus width operations.

Abstract translation: 在数字处理系统中实现使用多项式扩展近似数学函数的方法。 为了高精度降低参数大于pi / 4的多项式，提出了部分余数运算。 该方法可以在具有所需结果的精度的大约一半宽度的总线的处理器中实现。 临时寄存器用于存储中间结果。 通过连续的半总线宽度操作获得完整的总线宽度精度。

公开(公告)号：US5337265A

公开(公告)日：1994-08-09

申请号：US981031

申请日：1992-11-24

Applicant: Bernard Desrosiers ,  Didier Louis ,  Andre Steimle

Inventor： Bernard Desrosiers ,  Didier Louis ,  Andre Steimle

IPC: G06F7/485 ,  G06F7/50

CPC classification number: G06F7/485

Abstract: A numeric data coprocessor having an execution unit adapted to efficiently execute addition/subtraction operations on floating-point numbers in compliance with the IEEE standard 754. The mantissa adder carry out bit resulting from the operation on two operands X and Y is directly concatenated with the mantissa adder result in the mantissa output register to be the MSB thereof. Simultaneously, a 1 is added to the exponent of operand X or Y with the highest value. The final result is found after normalizing, regardless of whether the carry out bit is 1 or 0.In its hardware embodiment, taking for example the 80-bit double extended precision IEEE format, the mantissa output register has 68 positions. The 68th supplementary position is fed by the carry out bit generated by the mantissa adder at the "carry out" output. The "Force Carry" input of the exponent adder is activated by the control logic circuitry to add a 1 to the operand exponent with the highest value.

Abstract translation: 一种具有执行单元的数字数据协处理器，其适于根据IEEE标准754有效地对浮点数执行加法/减法运算。尾数加法器执行由两个操作数X和Y上的操作产生的位直接连接到 尾数加法器将尾数输出寄存器作为其MSB。 同时，对于具有最高值的操作数X或Y的指数加1。 无论进位位是1还是0，都在归一化后找到最终结果。在其硬件实施例中，例如采用80位双倍扩展精度IEEE格式，尾数输出寄存器具有68个位置。 第68个补充位置由在“进位输出”输出处由尾数加法器产生的进位位进给。 指数加法器的“强制进位”输入由控制逻辑电路激活，以将最大值的操作数指数加1。

公开(公告)号：US20090019326A1

公开(公告)日：2009-01-15

申请号：US12154188

申请日：2008-05-21

Applicant: Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

Inventor： Gerard Boudon ,  Didier Malcavet ,  David Pereira ,  Andre Steimle

IPC: G06F11/00

CPC classification number: G01R31/3171

Abstract: A self-synchronizing data bus analyser is provided which can include a generator linear feedback shift register (LFSR) to generate a first data set, and can include a receiver LFSR to generate a second data set. The data bus analyzer may also include a bit sampler to sample the first data set received through a data bus coupled to the generator LFSR and output a sampled first data set. A comparator can be included to compare the sampled first data set with the second data set generated by the receiver LFSR and provide a signal to the receiver LFSR to adjust a phase of the receiver LFSR until the second data set is substantially the same as the first data set.

Abstract translation: 提供了一种自同步数据总线分析器，其可以包括发生器线性反馈移位寄存器（LFSR）以产生第一数据集，并且可以包括接收器LFSR以生成第二数据集。 数据总线分析器还可以包括比特采样器，以对通过耦合到发生器LFSR的数据总线接收的第一数据集进行采样，并输出采样的第一数据集。 可以包括比较器以将采样的第一数据集与由接收机LFSR生成的第二数据集进行比较，并向接收机LFSR提供信号以调整接收机LFSR的相位，直到第二数据组与第一数据集基本相同 数据集。

公开(公告)号：US20050212932A1

公开(公告)日：2005-09-29

申请号：US10906333

申请日：2005-02-15

Applicant: Andre Steimle ,  Bernard Jung

Inventor： Andre Steimle ,  Bernard Jung

IPC: G06F1/32 ,  H04N5/374 ,  H04N9/64

CPC classification number: H04N5/23241 ,  H04N5/335

Abstract: The image sensing device interface unit attached to an image sensing device has dedicated means to detect a complete missing line and to perform clock gating of circuits for power management self-optimization. For each image frame, the time interval between start of line 1 and start of line 2 is computed and stored in a first register. The time interval between any other pair of two consecutive lines is also computed and stored in a second register. The stored values are compared, and if the value in the second register is greater than in the first register, a complete missing line has been detected and the gated clock used in said circuits is switched off for power saving. The interface unit can adapt to any type of sensor and does not require the help of any processor to perform the power saving function.

Abstract translation: 附加到图像感测装置的图像感测装置接口单元具有专用装置，用于检测完整的缺失线并执行用于电源管理自优化的电路的时钟选通。 对于每个图像帧，计算行1开始和行2开始之间的时间间隔并将其存储在第一寄存器中。 任何其他两对连续行之间的时间间隔也被计算并存储在第二寄存器中。 比较存储的值，并且如果第二寄存器中的值大于第一寄存器中的值，则检测到完整的缺失行，并且在所述电路中使用的门控时钟被关闭以进行省电。 接口单元可以适应任何类型的传感器，并且不需要任何处理器的帮助来执行省电功能。

公开(公告)号：US06535862B1

公开(公告)日：2003-03-18

申请号：US09411289

申请日：1999-10-04

Applicant: Didier Louis ,  Andre Steimle

Inventor： Didier Louis ,  Andre Steimle

IPC: G06N302

CPC classification number: G06K9/6271 ,  G06K9/6262 ,  G06N3/063

Abstract: A diagnostic method engages all the neurons of an artificial neural network (ANN) based on mapping an input space defined by vector components based on category, context, and actual field of influence (AIF). The method includes the steps loading the components of a first and second input vectors into the ANN; engaging all the neurons of a same prototype; having all the neurons compute their own distance between the respective prototypes and the second input vector (which should be the same if the neurons were good); determining the minimum distance Dmin and comparing Dmin with a distance D measured between the first and the second input vectors. If Dmin

Abstract translation: 基于对基于类别，上下文和实际影响领域（AIF）的矢量分量定义的输入空间的映射，诊断方法接合人造神经网络（ANN）的所有神经元。 该方法包括将第一和第二输入向量的分量加载到ANN中的步骤; 吸引同一原型的所有神经元; 所有的神经元都计算它们自己在各个原型之间的距离和第二个输入向量（如果神经元是好的，它们应该相同）; 确定最小距离Dmin并将Dmin与在第一和第二输入向量之间测量的距离D进行比较。 如果Dmin = D，ANN的良好神经元被取消选择，防止良好的神经元进一步学习/识别处理; 并重复前面的步骤直到ANN为空。 本方法提供了以仅仅几个逻辑门为代价的形成ANN的神经元的快速廉价的完整性诊断。