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公开(公告)号：US20130275720A1
公开(公告)日：2013-10-17
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。
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公开(公告)号：US20080250275A1
公开(公告)日：2008-10-09
申请号：US11697428
申请日：2007-04-06
申请人： Kevin R. Walker , John H. Mylius
发明人： Kevin R. Walker , John H. Mylius
IPC分类号： G06F11/34
CPC分类号： G06F11/3636 , G06F11/3476
摘要： In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.
摘要翻译： 在一个实施例中，集成电路包括被配置为输出程序计数器（PC）跟踪记录的第一处理器，其中PC跟踪记录提供指示由第一处理器退休的指令的PC的数据。 集成电路还包括跟踪记录的第二源，以及耦合以从第一处理器接收PC跟踪记录和来自第二源的跟踪记录的跟踪单元。 跟踪单元包括跟踪单元，跟踪单元被配置为存储来自第二个源的PC跟踪记录和跟踪记录。 跟踪单元被配置为根据记录的接收顺序将跟踪记录和跟踪记录中的跟踪记录交错在跟踪存储器中。
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公开(公告)号：US20130339671A1
公开(公告)日：2013-12-19
申请号：US13517865
申请日：2012-06-14
CPC分类号： G06F9/30043 , G06F9/30181 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/384
摘要： A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction.
摘要翻译： 一种用于减少加载操作延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的加载指令是否符合转换为零周期加载操作的资格。 如果是这样，则控制逻辑将与旧的从属存储指令的源操作数相关联的物理寄存器标识分配给加载指令的目的地操作数。 此外，寄存器重命名单元标记加载指令以防止其从存储器读取与存储指令的源操作数相关联的数据。 由于重复重命名，该数据可能会从物理寄存器文件转发到更年轻且取决于加载指令的指令。
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公开(公告)号：US20130191677A1
公开(公告)日：2013-07-25
申请号：US13355023
申请日：2012-01-20
CPC分类号： G06F1/10 , G06F1/3237 , H03K19/0016 , Y02D10/128
摘要： A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.
摘要翻译： 公开了一种用于在空闲时间期间抖动时钟信号的系统和方法。 集成电路（IC）包括多个功能单元和时钟树。 时钟树包括根电平时钟门控电路，多个区域时钟门控电路和多个叶电平时钟门控电路。 根电平时钟门控电路被耦合以将操作时钟信号分配给区域时钟门控电路，而区域时钟门控电路各自被配置为将操作时钟信号分配给对应的叶级别门控时钟信号 电路。 IC还可以包括控制单元，其被配置为监视来自每个功能单元的活动水平和指示。 如果IC空闲，则控制单元可以使根时钟选通电路对时钟信号进行抖动，其中抖动包括降低工作时钟信号的占空比和有效频率。
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公开(公告)号：US07984338B2
公开(公告)日：2011-07-19
申请号：US12774346
申请日：2010-05-05
申请人： Kevin R. Walker , John H. Mylius
发明人： Kevin R. Walker , John H. Mylius
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3476
摘要： In one embodiment, an integrated circuit comprises a first processor configured to output program counter (PC) trace records, wherein PC trace records provide data indicating the PCs of instructions retired by the first processor. The integrated circuit further comprises a second source of trace records, and a trace unit coupled to receive the PC trace records from the first processor and the trace records from the second source. The trace unit comprises a trace memory into which the trace unit is configured to store the PC trace records and trace records from the second source. The trace unit is configured to interleave the PC trace records and the trace records from the second source in the trace memory according to the order of receipt of the records.
摘要翻译： 在一个实施例中，集成电路包括被配置为输出程序计数器（PC）跟踪记录的第一处理器，其中PC跟踪记录提供指示由第一处理器退休的指令的PC的数据。 集成电路还包括跟踪记录的第二源，以及耦合以从第一处理器接收PC跟踪记录和来自第二源的跟踪记录的跟踪单元。 跟踪单元包括跟踪单元，跟踪单元被配置为存储来自第二个源的PC跟踪记录和跟踪记录。 跟踪单元被配置为根据记录的接收顺序将跟踪记录和跟踪记录中的跟踪记录交错在跟踪存储器中。
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公开(公告)号：US09996348B2
公开(公告)日：2018-06-12
申请号：US13517865
申请日：2012-06-14
CPC分类号： G06F9/30043 , G06F9/30181 , G06F9/3826 , G06F9/3834 , G06F9/3838 , G06F9/384
摘要： A system and method for reducing the latency of load operations. A register rename unit within a processor determines whether a decoded load instruction is eligible for conversion to a zero-cycle load operation. If so, control logic assigns a physical register identifier associated with a source operand of an older dependent store instruction to the destination operand of the load instruction. Additionally, the register rename unit marks the load instruction to prevent it from reading data associated with the source operand of the store instruction from memory. Due to the duplicate renaming, this data may be forwarded from a physical register file to instructions that are younger and dependent on the load instruction.
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17.发明申请LOW POWER AND HIGH PERFORMANCE PHYSICAL REGISTER FREE LIST IMPLEMENTATION FOR MICROPROCESSORS 有权低功耗和高性能物理寄存器免费列表实现微处理器公开(公告)号：US20140013085A1
公开(公告)日：2014-01-09
申请号：US13541351
申请日：2012-07-03
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/384
摘要： A system and method for reducing latency and power of register renaming. A free list in processor includes multiple banks for indicating availability of register identifiers used for register renaming. A register rename unit receives one or more destination architectural registers to rename with physical register identifiers. Responsive to determining the multiple banks within the free list are unbalanced with available physical register identifiers, one or more returning physical register identifiers are assigned to the destination architectural registers before assigning any physical register identifiers from any bank of the multiple banks with a lowest number of available physical register identifiers. A returning physical register identifier is a physical register identifier that is available again for assignment to a destination architectural register but not yet indicated in the free list as available. Each of the banks includes a single bit width decoded vector for indicating availability of given physical register identifiers.
摘要翻译： 一种用于减少寄存器重命名的等待时间和功率的系统和方法。 处理器中的一个空白列表包括用于指示用于寄存器重命名的寄存器标识符的可用性的多个存储单元。 寄存器重命名单元接收一个或多个目的地体系结构寄存器以用物理寄存器标识符重命名。 响应于确定空闲列表中的多个存储体与可用的物理寄存器标识符不平衡，一个或多个返回物理寄存器标识符被分配给目的地架构寄存器，然后从具有最低数量 可用的物理寄存器标识符。 返回的物理寄存器标识符是物理寄存器标识符，可以再次用于分配到目的地架构寄存器，但尚未在可用的空闲列表中指示。 每个存储体包括用于指示给定物理寄存器标识符的可用性的单个位宽解码向量。
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18.发明授权公开(公告)号：US07003648B2
公开(公告)日：2006-02-21
申请号：US10109255
申请日：2002-03-28
IPC分类号： G06F15/82 , G06F15/163
CPC分类号： G06F9/3855 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3857
摘要： A multi-threaded processor provides for efficient flow-control from a pool of un-executed stores in an instruction queue to a store queue. The processor also includes similar capabilities with respect to load instructions. The processor includes logic organized into a plurality of thread processing units (“TPUs”) and allocation logic that monitors each TPUs demand for entries in the store queue. Demand is determined by subtracting an adjustable threshold value from the most recently assigned store identifier value. If the difference between the most recently assigned instruction identifier for a TPU and the TPU's threshold is non-zero, then it is determined that the TPU has demand for at least one entry in the store queue. The allocation logic includes arbitration logic that determines which one of a plurality of TPUs with store queue demand should be allocated a free entry in the store queue.
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公开(公告)号：US09575754B2
公开(公告)日：2017-02-21
申请号：US13447651
申请日：2012-04-16
申请人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
发明人： James B. Keller , John H. Mylius , Conrado Blasco-Allue , Gerard R. Williams, III , Suparn Vats
CPC分类号： G06F9/30032 , G06F9/384
摘要： A system and method for reducing the latency of data move operations. A register rename unit within a processor determines whether a decoded move instruction is eligible for a zero cycle move operation. If so, control logic assigns a physical register identifier associated with a source operand of the move instruction to the destination operand of the move instruction. Additionally, the register rename unit marks the given move instruction to prevent it from proceeding in the processor pipeline. Further maintenance of the particular physical register identifier may be done by the register rename unit during commit of the given move instruction.
摘要翻译： 一种用于减少数据移动操作的延迟的系统和方法。 处理器内的寄存器重命名单元确定解码的移动指令是否符合零周期移动操作的资格。 如果是这样，则控制逻辑将与移动指令的源操作数相关联的物理寄存器标识分配给移动指令的目的地操作数。 此外，寄存器重命名单元标记给定的移动指令以防止其在处理器管线中继续进行。 特定物理寄存器标识符的进一步维护可以在给定移动指令的提交期间由寄存器重命名单元完成。
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公开(公告)号：US09430243B2
公开(公告)日：2016-08-30
申请号：US13460268
申请日：2012-04-30
IPC分类号： G06F9/38
CPC分类号： G06F9/384 , G06F9/3832 , G06F9/3857
摘要： A system and method for efficiently reducing the latency of initializing registers. A register rename unit within a processor determines whether prior to an execution pipeline stage it is known a decoded given instruction writes a particular numerical value in a destination operand. An example is a move immediate instruction that writes a value of 0 in its destination operand. Other examples may also qualify. If the determination is made, a given physical register identifier is assigned to the destination operand, wherein the given physical register identifier is associated with the particular numerical value, but it is not associated with an actual physical register in a physical register file. The given instruction is marked to prevent it from proceeding to an execution pipeline stage. When the given physical register identifier is used to read the physical register file, no actual physical register is accessed.
摘要翻译： 一种用于有效减少初始化寄存器的延迟的系统和方法。 处理器内的寄存器重命名单元确定在执行流水线阶段之前是否已知解码的给定指令将目标操作数中的特定数值写入。 一个示例是在其目标操作数中写入值0的移动即时指令。 其他示例也可能符合条件。 如果确定，给定的物理寄存器标识符被分配给目的地操作数，其中给定的物理寄存器标识符与特定数值相关联，但是它不与物理寄存器文件中的实际物理寄存器相关联。 给定的指令被标记为防止它进入执行流水线阶段。 当给定的物理寄存器标识符用于读取物理寄存器文件时，不会访问实际的物理寄存器。
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