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公开(公告)号：US08769332B2
公开(公告)日：2014-07-01
申请号：US13355023
申请日：2012-01-20
CPC分类号： G06F1/10 , G06F1/3237 , H03K19/0016 , Y02D10/128
摘要： A system and method for dithering a clock signal during idle times is disclosed. An integrated circuit (IC) includes a number of functional units and a clock tree. The clock tree includes a root level clock-gating circuit, a number of regional clock-gating circuits, and a number of leaf level clock-gating circuits. The root level clock-gating circuit is coupled to distribute an operating clock signal to the regional clock-gating circuits, while the regional clock-gating circuits are each configured to distribute the operating clock signal to correspondingly coupled ones of the leaf level clock-gating circuits. The IC may further include a control unit configured to monitor activity levels and indications from each of the functional units. The control unit may cause the root clock-gating circuit to dither the clock signal if the IC is idle, wherein dithering includes reducing the duty cycle and the effective frequency of the operating clock signal.
摘要翻译： 公开了一种用于在空闲时间期间抖动时钟信号的系统和方法。 集成电路（IC）包括多个功能单元和时钟树。 时钟树包括根电平时钟门控电路，多个区域时钟门控电路和多个叶电平时钟门控电路。 根电平时钟门控电路被耦合以将操作时钟信号分配给区域时钟门控电路，而区域时钟选通电路被配置为将操作时钟信号分配给对应的叶级别门控时钟信号 电路。 IC还可以包括控制单元，其被配置为监视来自每个功能单元的活动水平和指示。 如果IC空闲，则控制单元可以使根时钟选通电路对时钟信号进行抖动，其中抖动包括降低工作时钟信号的占空比和有效频率。
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公开(公告)号：US20130042135A1
公开(公告)日：2013-02-14
申请号：US13208669
申请日：2011-08-12
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.
摘要翻译： 一种用于在片上系统（SOC）上有效同步多个处理核心的系统和方法。 SOC包括一个中断控制器和多个处理核心。 中断控制器包括主时计计数器。 SOC包括多个本地时基计数器，每个计数器分别耦合到相应的一个处理核心。 同步逻辑块用于更新本地计数器。 这些块从中断控制器接收位的子集。 位的子集表示主计数器的少数位的总数少于主计数器的位数的最低有效位数。 逻辑块根据所接收的位子集的改变来更新相关联的本地计数器。 在中断控制器中的主计数器的值与处理核心中的本地计数器之间可能存在差异。 然而，这种差异可能是一个恒定的值。
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公开(公告)号：US08571216B2
公开(公告)日：2013-10-29
申请号：US12325613
申请日：2008-12-01
申请人： Conrad H. Ziesler
发明人： Conrad H. Ziesler
IPC分类号： G06F21/00
CPC分类号： H04N19/88 , H04N7/1675 , H04N19/423 , H04N21/234327 , H04N21/23476 , H04N21/44055 , H04N21/835
摘要： In an embodiment, an integrated circuit comprises a decompressor, an encrypt unit, and an on-chip image buffer coupled to the decompressor and the encrypt unit. The decompressor is configured to receive a compressed video stream, and to reconstruct a first frame of the video stream in the on-chip buffer. The encrypt unit is configured to generate one or more pixel block streams from pixel blocks of the first frame in the on-chip buffer according to sequence data describing an order of access of the pixel blocks to reconstruct subsequent frames of the video stream. The sequence data was previously generated via processing of the video stream by the integrated circuit, and the encrypt unit is configured to encrypt the pixel block streams to be written to an external memory. In an embodiment, an integrated circuit comprises a decrypt unit configured to decrypt an encrypted, compressed video stream; an on-chip buffer; and a decompressor coupled to the decrypt unit and the on-chip buffer. The decompressor is configured decompress the video stream, and to store a first portion of each of a first plurality of frames decompressed from the video stream in the on-chip buffer. The decompressor is further configured to store a remaining portion of each of the first plurality of frames in an external memory, wherein each frame as stored in the external memory is incomplete because the first portion is not stored in the external memory.
摘要翻译： 在一个实施例中，集成电路包括解压缩器，加密单元和耦合到解压缩器和加密单元的片上图像缓冲器。 解压缩器被配置为接收压缩视频流，并且重建片上缓冲器中的视频流的第一帧。 加密单元被配置为根据描述像素块的访问顺序来重建视频流的后续帧的顺序数据从片上缓冲器中的第一帧的像素块生成一个或多个像素块流。 先前通过集成电路对视频流的处理产生序列数据，并且加密单元被配置为对要写入外部存储器的像素块流进行加密。 在一个实施例中，集成电路包括被配置为对加密的压缩视频流进行解密的解密单元; 一个片上缓冲区; 以及耦合到解密单元和片上缓冲器的解压缩器。 解压缩器被配置为解压缩视频流，并且将从视频流解压缩的第一多个帧中的每一个的第一部分存储在片上缓冲器中。 解压缩器还被配置为将第一多个帧中的每一个的剩余部分存储在外部存储器中，其中存储在外部存储器中的每个帧不完整，因为第一部分不存储在外部存储器中。
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公开(公告)号：US20120314516A1
公开(公告)日：2012-12-13
申请号：US13157433
申请日：2011-06-10
IPC分类号： G11C7/00
CPC分类号： G11C29/04 , G11C8/08 , G11C29/30 , G11C2029/1202
摘要： A memory may include a memory array, a plurality of control circuits, and a plurality of isolation circuits. The plurality of control circuits may be configured to generate control signals for the memory array. For example, the plurality of control circuits may include a plurality of word line driver circuits. The plurality of isolation circuits may be configured to receive the control signals from the plurality of control circuits and a plurality of isolation signals. A first isolation signal may correspond to the plurality of word line driver circuits and at least one second isolation signal may correspond to other ones of the plurality of control circuits. The first isolation signal and the second isolation signal may be independently controlled during memory tests to detect stuck-at faults associated with the plurality of isolation signals.
摘要翻译： 存储器可以包括存储器阵列，多个控制电路和多个隔离电路。 多个控制电路可以被配置为产生用于存储器阵列的控制信号。 例如，多个控制电路可以包括多个字线驱动电路。 多个隔离电路可以被配置为从多个控制电路接收控制信号和多个隔离信号。 第一隔离信号可以对应于多个字线驱动器电路，并且至少一个第二隔离信号可以对应于多个控制电路中的其它控制电路。 可以在存储器测试期间独立地控制第一隔离信号和第二隔离信号，以检测与多个隔离信号相关联的卡入故障。
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公开(公告)号：US08169764B2
公开(公告)日：2012-05-01
申请号：US12390085
申请日：2009-02-20
IPC分类号： H02H5/00
CPC分类号： H03K19/00369 , G06F1/206 , G06F1/3203 , Y02D10/16
摘要： In an embodiment, an integrated circuit comprises a plurality of temperature sensors and a power manager coupled thereto. The temperature sensors are physically distributed over an area of the integrated circuit that is occupied by logic circuitry implementing the operations for which the integrated circuit is designed. The power manager is configured to transmit a power supply voltage request to an external power supply module, the power supply voltage request indicating a requested magnitude of the power supply voltage for the integrated circuit. The power manager is configured to modify the requested magnitude responsive to indications from each of the plurality of temperatures sensors that represent a temperature of the integrated circuit sensed by each of the plurality of temperature sensors.
摘要翻译： 在一个实施例中，集成电路包括多个温度传感器和耦合到其上的功率管理器。 温度传感器物理分布在由集成电路设计的逻辑电路所占据的集成电路的一个区域上，该逻辑电路实现集成电路的设计。 功率管理器被配置为向外部电源模块发送电源电压请求，电源电压请求指示集成电路的电源电压的请求大小。 功率管理器被配置为响应于表示由多个温度传感器中的每一个感测的集成电路的温度的多个温度传感器中的每一个的指示来修改所请求的幅度。
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6.发明申请公开(公告)号：US20110198942A1
公开(公告)日：2011-08-18
申请号：US12705837
申请日：2010-02-15
IPC分类号： H01H35/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit includes a power gated block and a power manager circuit. The power manager circuit is configured to provide a block enable signal and at least one select signal to the power gated block. The power manager may generate the select signal responsive to various parameters that affect the speed of the integrated circuit, such as power supply voltage magnitude, operating temperature, and/or process corner. The power gated block may control the rate at which power switches are enabled based on the select signal or signals. For example, the power switches may be enabled in a more parallel or more serial fashion and/or the drive strength of block enable buffering to the power switches may be varied. In another embodiment, the power manager circuit may assert multiple block enables to the power gated block (which are connected to separate sets of power switches), and may control the timing of assertion of the enables to control the rate at which power switches are enabled.
摘要翻译： 在一个实施例中，集成电路包括电源门控块和功率管理器电路。 功率管理器电路被配置为向电源门控块提供块使能信号和至少一个选择信号。 功率管理器可以响应于影响集成电路的速度的各种参数（例如电源电压幅度，工作温度和/或过程角）来产生选择信号。 电源门控块可以基于选择信号或信号来控制使能电源开关的速率。 例如，功率开关可以以更并行或更串联的方式启用和/或可以改变对功率开关的块使能缓冲的驱动强度。 在另一个实施例中，功率管理器电路可以将功率门控块（其连接到单独的功率开关组）断言多个块使能，并且可以控制用于控制功率开关被使能的速率的使能的定时 。
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公开(公告)号：US20110198941A1
公开(公告)日：2011-08-18
申请号：US12705834
申请日：2010-02-15
申请人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
发明人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
IPC分类号： H01H35/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
摘要翻译： 在一个实施例中，集成电路可以包括一个或多个功率管理块和功率管理器电路。 功率管理器电路可以被配置为为每个功率管理块和块使能时钟生成块使能。 功率管理块可以在功率管理块中产生各种功率开关的本地块使能，交错块启用超过两个或更多个块使能时钟周期。 特别地，功率管理块可以包括从功率管理器电路接收块使能的一组串联的触发器。 每个触发器的输出可以耦合到相应的一组电源开关，并且可以启用这些开关。 因此可以控制由于使能和/或禁用功率管理块而引起的电流流动的变化。 在一个实施例中，块使能时钟的频率可以被设置为独立于集成电路中的处理，电压和温度条件的限定值。
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公开(公告)号：US07355454B2
公开(公告)日：2008-04-08
申请号：US11153135
申请日：2005-06-15
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/0019 , H02M3/158
摘要： A boost circuit is disclosed that includes a plurality of transistors connected between complementary phases of a clock signal. The boost circuit further includes a first electrical node connected between at least two of the plurality of transistors wherein the plurality of transistors are configured to generate a second voltage from a first voltage at the electrical node in response to the clock signal.
摘要翻译： 公开了一种升压电路，其包括连接在时钟信号的互补相位之间的多个晶体管。 升压电路还包括连接在所述多个晶体管中的至少两个晶体管之间的第一电节点，其中所述多个晶体管被配置为响应于所述时钟信号从所述电节点处的第一电压产生第二电压。
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公开(公告)号：US08977881B2
公开(公告)日：2015-03-10
申请号：US13208669
申请日：2011-08-12
IPC分类号： G06F1/12
CPC分类号： G06F1/12
摘要： A system and method for efficiently synchronizing multiple processing cores on a system-on-a-chip (SOC). A SOC includes an interrupt controller and multiple processing cores. The interrupt controller includes a main time base counter. The SOC includes multiple local time base counters, each coupled to a respective one of the processing cores. Synchronization logic blocks are used to update the local counters. These blocks receive a subset of bits from the interrupt controller. The subset of bits represents a number of least significant bits of the main counter less than a total number of bits for the main counter. The logic blocks update an associated local counter according to changes to the received subset of bits. A difference may exist between values of the main counter in the interrupt controller and the local counter in the processing core. However, this difference may be a constant value.
摘要翻译： 一种用于在片上系统（SOC）上有效同步多个处理核心的系统和方法。 SOC包括一个中断控制器和多个处理核心。 中断控制器包括主时计计数器。 SOC包括多个本地时基计数器，每个计数器分别耦合到相应的一个处理核心。 同步逻辑块用于更新本地计数器。 这些块从中断控制器接收位的子集。 位的子集表示主计数器的少数位的总数少于主计数器的位数的最低有效位数。 逻辑块根据所接收的位子集的改变来更新相关联的本地计数器。 在中断控制器中的主计数器的值与处理核心中的本地计数器之间可能存在差异。 然而，这种差异可能是一个恒定的值。
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公开(公告)号：US08362805B2
公开(公告)日：2013-01-29
申请号：US12705834
申请日：2010-02-15
申请人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
发明人： Shingo Suzuki , Vincent R. von Kaenel , Toshinari Takayanagi , Conrad H. Ziesler , Daniel C. Murray
IPC分类号： H03K193/00 , H03B21/00
CPC分类号： H03K19/0016 , Y10T307/766
摘要： In an embodiment, an integrated circuit may include one or more power managed blocks and a power manager circuit. The power manager circuit may be configured to generate a block enable for each power managed block and a block enable clock. The power managed block may generate local block enables to various power switches in the power managed block, staggering the block enables over two or more block enable clock cycles. In particular, the power managed block may include a set of series-connected flops that receive the block enable from the power manager circuit. The output of each flop may be coupled to a respective set of power switches and may enabled those switches. The change in current flow due to enabling and/or disabling the power managed block may thus be controlled. In an embodiment, the frequency of the block enable clock may be set to a defined value independent of process, voltage, and temperature conditions in the integrated circuit.
摘要翻译： 在一个实施例中，集成电路可以包括一个或多个功率管理块和功率管理器电路。 功率管理器电路可以被配置为为每个功率管理块和块使能时钟生成块使能。 功率管理块可以在功率管理块中产生各种功率开关的本地块使能，交错块启用超过两个或更多个块使能时钟周期。 特别地，功率管理块可以包括从功率管理器电路接收块使能的一组串联的触发器。 每个触发器的输出可以耦合到相应的一组电源开关，并且可以启用这些开关。 因此可以控制由于使能和/或禁用功率管理块而引起的电流流动的变化。 在一个实施例中，块使能时钟的频率可以被设置为独立于集成电路中的处理，电压和温度条件的限定值。
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