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11.
公开(公告)号:US10853199B2
公开(公告)日:2020-12-01
申请号:US16136189
申请日:2018-09-19
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan , Tudor Antoniu
Abstract: Disclosed are techniques for managing context information for data stored within a computing device. According to some embodiments, the method can include the steps of (1) loading, into a volatile memory of the computing device, the context information from a non-volatile memory of the computing device, where the context information is separated into a plurality of portions, and each portion of the plurality of portions is separated into a plurality of sub-portions, (2) writing transactions into a log stored within the non-volatile memory, and (3) each time a condition is satisfied: identifying a next sub-portion to be processed, where the next sub-portion is included in the plurality of sub-portions of a current portion being processed, identifying a portion of the context information that corresponds to the next sub-portion, converting the portion from a first format to a second format, and writing the portion into the non-volatile memory.
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公开(公告)号:US11494107B2
公开(公告)日:2022-11-08
申请号:US16381969
申请日:2019-04-11
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan , Evgeny Televitckiy
Abstract: Disclosed herein are techniques for managing parity information for data stored on a storage device. A method includes (1) receiving a request to store data into the storage device, (2) storing portions of the data in data pages included in stripes in a band of the storage device, where a respective data page is stored on a respective different die of a respective stripe, (3) determining primary parity information for a first stripe including a subset of the data pages, (4) storing the primary parity information in a primary parity page included in a second stripe in the stripes in the band, where the primary parity page is disposed on a next available die relative to dies storing the data pages, (5) determining secondary parity information for the second stripe, and (6) storing the secondary parity information in a secondary parity page included in the stripes in the band.
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公开(公告)号:US11132145B2
公开(公告)日:2021-09-28
申请号:US16124154
申请日:2018-09-06
Applicant: Apple Inc.
Inventor: Yuhua Liu , Andrew W. Vogan , Matthew J. Byom , Alexander Paley
Abstract: Disclosed herein are techniques for reducing write amplification when processing write commands directed to a non-volatile memory. According to some embodiments, the method can include the steps of (1) receiving a first plurality of write commands and a second plurality of write commands, where the first plurality of write commands and the second plurality of write commands are separated by a fence command (2) caching the first plurality of write commands, the second plurality of write commands, and the fence command, and (3) in accordance with the fence command, and in response to identifying that at least one condition is satisfied: (i) issuing the first plurality of write commands to the non-volatile memory, (ii) issuing the second plurality of write commands to the non-volatile memory, and (iii) updating log information to reflect that the first plurality of write commands precede the second plurality of write commands.
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公开(公告)号:US11094381B2
公开(公告)日:2021-08-17
申请号:US16429021
申请日:2019-06-02
Applicant: Apple Inc.
Inventor: Muhammad N. Ashraf , Alexander Paley , Yuhua Liu , Vadim Khmelnitsky , Matthew J. Byom
Abstract: Systems and methods for managing non-volatile memory devices are provided. Embodiments discussed herein provide rapid restart protection for journaling system. The rapid restart protection prevents the NVM from experiencing memory saturation when the NVM system is being forced to handle multiple successive restarts.
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15.
公开(公告)号:US10162561B2
公开(公告)日:2018-12-25
申请号:US15190216
申请日:2016-06-23
Applicant: Apple Inc.
Inventor: Alexander Paley , Yuhua Liu
IPC: G06F3/06 , G06F12/1009 , G06F12/02 , G06F11/14
Abstract: An apparatus includes an interface and a processor. The interface is configured to communicate with a non-volatile memory. The processor is configured to hold a translation table that maps between logical addresses and respective physical addresses in the non-volatile memory, to back-up to the non-volatile memory a baseline version of the translation table in one or more bulks, to additionally back-up to the non-volatile memory one or more incremental updates, which specify changes relative to the baseline version of the translation table caused by subsequent storage operations, to determine a maximal number of the incremental updates that, when recovered together with the baseline version from the non-volatile memory and replayed in the processor, meets a target recovery time of the translation table, and to set a number of the backed-up incremental updates to not exceed the maximal number.
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公开(公告)号:US09990023B2
公开(公告)日:2018-06-05
申请号:US15219984
申请日:2016-07-26
Applicant: Apple Inc.
Inventor: Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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