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公开(公告)号：US20170277245A1
公开(公告)日：2017-09-28
申请号：US15219984
申请日：2016-07-26
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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Patent Agency Ranking
公开(公告)号：US09858990B2
公开(公告)日：2018-01-02
申请号：US14574527
申请日：2014-12-18
Applicant: APPLE INC.
Inventor： Liran Erez , Guy Ben-Yehuda , Avraham (Poza) Meir , Ori Isachar
CPC classification number: G11C11/5628 , G11C7/1045 , G11C7/1063
Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.
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公开(公告)号：US20160179373A1
公开(公告)日：2016-06-23
申请号：US14574527
申请日：2014-12-18
Applicant: APPLE INC.
Inventor： Liran Erez , Guy Ben-Yehuda , Avraham (Poza) Meir , Ori Isachar
IPC: G06F3/06
CPC classification number: G11C11/5628 , G11C7/1045 , G11C7/1063
Abstract: An apparatus includes a register memory and circuitry. The register memory is configured to hold a minimal value specified for a performance measure of a given type of memory access commands, whose actual performance measures vary among memory devices. The circuitry is configured to receive a memory access command of the given type, to execute the received memory access command in one or more memory devices, and to acknowledge the memory access command not before reaching the minimal value stored in the register memory.
Abstract translation: 一种装置包括寄存器存储器和电路。 寄存器存储器被配置为保持为给定类型的存储器访问命令的性能测量指定的最小值，其实际性能测量在存储器设备之间变化。 电路被配置为接收给定类型的存储器访问命令，以在一个或多个存储器设备中执行接收的存储器访问命令，并且在达到存储在寄存器存储器中的最小值之前确认存储器访问命令。
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公开(公告)号：US09361951B2
公开(公告)日：2016-06-07
申请号：US14468661
申请日：2014-08-26
Applicant: Apple Inc.
Inventor： Naftali Sommer , Stas Mouler , Eyal Gurgi , Yoav Kasorla , Liran Erez
CPC classification number: G11C5/14 , G11C5/145 , G11C5/147 , G11C16/10 , G11C16/12 , G11C16/30 , G11C16/32
Abstract: A method includes, in a storage system that includes multiple memory devices, holding a definition of a given type of storage command. Multiple storage commands of the given type are executed in the memory devices, such that an actual current consumption of each storage command deviates from a nominal current waveform defined for the given type by no more than a predefined deviation, and such that each storage command is preceded by a random delay.
Abstract translation: 一种方法包括在包括多个存储设备的存储系统中，保持给定类型的存储命令的定义。 给定类型的多个存储命令在存储器件中被执行，使得每个存储命令的实际电流消耗偏离为给定类型定义的额定电流波形不超过预定义的偏差，并且使得每个存储命令是 之前是随机延迟。
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公开(公告)号：US09990023B2
公开(公告)日：2018-06-05
申请号：US15219984
申请日：2016-07-26
Applicant: Apple Inc.
Inventor： Alexander Paley , Andrew W. Vogan , Eran Sandel , Lior Mouler , Liran Erez , Matthew J. Byom , Muhammad N. Ashraf , Roman Guy
CPC classification number: G06F1/3275 , G06F1/263 , G06F1/30 , G06F1/3287 , G06F11/00
Abstract: Systems and methods for handling sudden power failures in non-volatile memory devices such as solid state drives are provided by having the non-volatile memory device boot up in a low power write mode, which limits substantially all programming operations to a single level cell (SLC) mode, as opposed to a normal mode in which the programming operations can be performed in a multi-level cell (MLC) mode. Thus, if the system experiences a sudden power failure when it is being powered solely by AC derived power and the battery is below a level sufficient for powering the device while it is programming in the SLC mode, data integrity will be preserved because the programming operation was being performed in SLC mode. The non-volatile memory device may be permitted to exit out the low power write mode into the normal mode when the charge level of the battery is sufficient for powering the system.
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公开(公告)号：US20150199999A1
公开(公告)日：2015-07-16
申请号：US14468661
申请日：2014-08-26
Applicant: Apple Inc.
Inventor： Naftali Sommer , Stas Mouler , Eyal Gurgi , Yoav Kasorla , Liran Erez
IPC: G11C5/14
CPC classification number: G11C5/14 , G11C5/145 , G11C5/147 , G11C16/10 , G11C16/12 , G11C16/30 , G11C16/32
Abstract: A method includes, in a storage system that includes multiple memory devices, holding a definition of a given type of storage command. Multiple storage commands of the given type are executed in the memory devices, such that an actual current consumption of each storage command deviates from a nominal current waveform defined for the given type by no more than a predefined deviation, and such that each storage command is preceded by a random delay.
Abstract translation: 一种方法包括在包括多个存储设备的存储系统中，保持给定类型的存储命令的定义。 给定类型的多个存储命令在存储器件中被执行，使得每个存储命令的实际电流消耗偏离为给定类型定义的额定电流波形不超过预定义的偏差，并且使得每个存储命令是 之前是随机延迟。
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