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    Display Driver Integrated Circuit Architecture With Shared Reference Voltages
    12.
    发明申请
    Display Driver Integrated Circuit Architecture With Shared Reference Voltages 有权
    显示驱动器集成电路架构与共享参考电压

    公开(公告)号：US20160203777A1

    公开(公告)日：2016-07-14

    申请号：US14993702

    申请日：2016-01-12

    Applicant: Apple Inc.

    Inventor： Kingsuk Brahma ,  David A. Stronks ,  Hopil Bae ,  Wei H. Yao

    IPC: G09G3/36

    CPC classification number: G01R27/205 ,  G09G3/006 ,  G09G3/2092 ,  G09G3/2096 ,  G09G3/3607 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/08 ,  G09G2320/0223

    Abstract: A display may have a substrate layer to which a display driver integrated circuit and flexible printed circuit are bonded. The display driver integrated circuit may be provided with switches and control circuitry for controlling the operation of the switches during bond resistance measurements. Test equipment may apply currents to pads in the display driver integrated circuit through contacts in the flexible printed circuit while controlling the switching circuitry. Based on these measurements and the measurement of trace resistances in a dummy flexible printed circuit, the test equipment may determine bond resistances for bonds between the display driver integrated circuit and the display substrate and between the flexible printed circuit and the display substrate. Displays may have master and slave display driver integrated circuits that share coarse reference voltages produced by the master from raw power supply voltages.

    Abstract translation: 显示器可以具有显示驱动器集成电路和柔性印刷电路结合到其上的基板层。 显示驱动器集成电路可以设置有用于在接合电阻测量期间控制开关的操作的开关和控制电路。 测试设备可以通过柔性印刷电路中的触点在显示驱动器集成电路中的焊盘上施加电流，同时控制开关电路。 基于这些测量和虚拟柔性印刷电路中的迹线电阻的测量，测试设备可以确定显示驱动器集成电路和显示器基板之间以及柔性印刷电路和显示器基板之间的结合的结合电阻。 显示器可以具有主从显示驱动器集成电路，其从原始电源电压共享由主机产生的粗参考电压。

    DEVICES AND METHODS FOR REDUCTION OF DISPLAY TO TOUCH CROSSTALK
    13.
    发明申请
    DEVICES AND METHODS FOR REDUCTION OF DISPLAY TO TOUCH CROSSTALK 有权
    用于减少显示器以触摸CROSSTALK的装置和方法

    公开(公告)号：US20150084911A1

    公开(公告)日：2015-03-26

    申请号：US14035104

    申请日：2013-09-24

    Applicant: APPLE INC.

    Inventor： David A. Stronks ,  Ahmad Al-Dahle ,  Wei H. Yao

    IPC: G06F3/044

    CPC classification number: G06F3/044 ,  G02F1/13624 ,  G02F2001/13606 ,  G06F3/0412 ,  G06F3/0416 ,  G06F3/0418 ,  G06F2203/04107 ,  G09G3/20 ,  G09G3/3655 ,  G09G2300/0847 ,  G09G2320/0209

    Abstract: Devices and methods for reducing display-to-touch crosstalk are provided. In or more examples, an electronic display panel may include a pixel. The pixel may include a pixel electrode, a common electrode, and a first transistor having a first source coupled to a data line, a first gate coupled to a gate line, and a first drain coupled to the pixel electrode. The first transistor may be configured to pass a data signal from the data line to the pixel electrode upon receipt of an activation signal from the gate line. The pixel may also include a second transistor having a second source coupled to the common electrode, a second gate coupled to the gate line, and a second drain coupled to a common voltage source. The second transistor may be configured to cause a parasitic capacitance between the gate line and the second drain of the second transistor instead of between the gate line and the first drain of the first transistor.

    Abstract translation: 提供了用于减少显示到触摸串扰的装置和方法。 在一个或多个示例中，电子显示面板可以包括像素。 像素可以包括像素电极，公共电极和具有耦合到数据线的第一源极的第一晶体管，耦合到栅极线的第一栅极和耦合到像素电极的第一漏极。 第一晶体管可以被配置为在从栅极线接收到激活信号时将数据信号从数据线传递到像素电极。 像素还可以包括具有耦合到公共电极的第二源极的第二晶体管，耦合到栅极线的第二栅极和耦合到公共电压源的第二漏极。 第二晶体管可以被配置为在第二晶体管的栅极线和第一漏极之间引起栅极线与第二晶体管的第二漏极之间的寄生电容。

    Systems and Methods for Reducing or Eliminating Mura Artifact Using Image Feedback
    14.
    发明申请
    Systems and Methods for Reducing or Eliminating Mura Artifact Using Image Feedback 有权
    使用图像反馈减少或消除Mura人工制品和方法

    公开(公告)号：US20130328843A1

    公开(公告)日：2013-12-12

    申请号：US13654231

    申请日：2012-10-17

    Applicant: APPLE INC.

    Inventor： Ahmad Al-Dahle ,  David A. Stronks ,  Hopil Bae

    IPC: G09G3/36 ,  G09G5/00 ,  G09G5/10

    CPC classification number: G09G3/3696 ,  G09G3/006 ,  G09G3/3655 ,  G09G2310/067 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2320/0693 ,  G09G2360/145

    Abstract: Systems, methods, and devices for calibrating an electronic display to reduce or eliminate a mura artifact are provided. The mura artifact may be due to differential behavior of common voltage layers (VCOMs) in the electronic display. One method for reducing or eliminating the mura artifact may involve setting pixels of the electronic display to a first gray level and measuring a luminance difference between light and dark areas of a mura artifact on the electronic display. A value of an operating parameter of the electronic display may be adjusted while monitoring the luminance difference measurement. A value of the operating parameter that causes the luminance difference measurement to be within a specified range of acceptable luminance difference measurement values may be stored in the electronic display.

    Abstract translation: 提供了用于校准电子显示器以减少或消除mura伪影的系统，方法和设备。 该mura伪影可能是由于电子显示器中的公共电压层（VCOM）的差异行为。 用于减少或消除凹陷假象的一种方法可以包括将电子显示器的像素设置为第一灰度级并且测量电子显示器上的mura伪影的亮区和暗区之间的亮度差。 可以在监视亮度差测量的同时调整电子显示器的操作参数的值。 导致亮度差测量在可接受的亮度差测量值的指定范围内的操作参数的值可以存储在电子显示器中。

    Devices and methods for reducing power consumption of a demultiplexer
    18.
    发明授权
    Devices and methods for reducing power consumption of a demultiplexer 有权
    用于降低解复用器的功耗的装置和方法

    公开(公告)号：US09311867B2

    公开(公告)日：2016-04-12

    申请号：US13890928

    申请日：2013-05-09

    Applicant: APPLE INC.

    Inventor： Sang Y. Youn ,  Hopil Bae ,  David A. Stronks ,  Kingsuk Brahma ,  Taif A. Syed

    IPC: G09G3/36

    CPC classification number: G09G3/3611 ,  G09G2310/0297 ,  G09G2330/021

    Abstract: The present disclosure relates to devices and methods for reducing power consumption of a display. One electronic display includes a first switch coupled between a first gate of a first transistor and a second gate of a second transistor to selectively connect the first gate to the second gate. The display includes a second switch coupled between the second gate of the second transistor and a third gate of a third transistor to selectively connect the second gate to the third gate. The display also includes driving circuitry that controls the first switch to connect the first gate to the second gate to share a first charge between the first and second gates. The driving circuitry also controls the second switch to connect the second gate to the third gate to share a second charge between the second and third gates. Accordingly, power consumption of the display may be reduced.

    Abstract translation: 本公开涉及用于降低显示器的功耗的装置和方法。 一个电子显示器包括耦合在第一晶体管的第一栅极和第二晶体管的第二栅极之间的第一开关，以选择性地将第一栅极连接到第二栅极。 显示器包括耦合在第二晶体管的第二栅极和第三晶体管的第三栅极之间的第二开关，以选择性地将第二栅极连接到第三栅极。 显示器还包括控制第一开关以将第一栅极连接到第二栅极以共享第一和第二栅极之间的第一电荷的驱动电路。 驱动电路还控制第二开关以将第二栅极连接到第三栅极，以在第二和第三栅极之间共享第二电荷。 因此，可以减少显示器的功耗。

    DEVICES AND METHODS FOR COMMON ELECTRODE MURA PREVENTION
    19.
    发明申请
    DEVICES AND METHODS FOR COMMON ELECTRODE MURA PREVENTION 有权
    用于常见电极防护的设备和方法

    公开(公告)号：US20130328847A1

    公开(公告)日：2013-12-12

    申请号：US13654242

    申请日：2012-10-17

    Applicant: APPLE INC.

    Inventor： Ahmad Al-Dahle ,  Hopil Bae ,  Sang Y. Youn ,  Yafei Bi ,  Wei H. Yao ,  David A. Stronks

    IPC: G09G5/00

    CPC classification number: G09G5/003 ,  G09G3/2092 ,  G09G2330/027 ,  G09G2330/06

    Abstract: Methods and devices employing mura prevention circuitry, are provided. In one example, a method may include supplying a first voltage pathway between a common electrode driver and a common electrode of an electronic display device and supplying a second voltage pathway between the common electrode driver and ground. Mura prevention circuitry may be supplied that activates the first voltage pathway when the electronic display device is turned on and an activation gate signal is provided from a gate corresponding to the common electrode driver. Further, the mura prevention circuitry may activate the second voltage pathway when the electronic display device is turned off or no activation gate signal is provided from the gate corresponding to the common electrode driver.

    Abstract translation: 提供了采用mura预防电路的方法和装置。 在一个示例中，方法可以包括在公共电极驱动器和电子显示装置的公共电极之间提供第一电压路径，并且在公共电极驱动器和地之间提供第二电压路径。 可以提供Mura防止电路，其在电子显示装置接通时激活第一电压通路，并且从对应于公共电极驱动器的门提供激活门信号。 此外，当电子显示装置关闭或从对应于公共电极驱动器的门提供激活栅极信号时，防护电路可以激活第二电压路径。

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