EARLY LOAD EXECUTION VIA CONSTANT ADDRESS AND STRIDE PREDICTION

    公开(公告)号:US20210049015A1

    公开(公告)日:2021-02-18

    申请号:US16539684

    申请日:2019-08-13

    Applicant: Apple Inc.

    Abstract: A system and method for efficiently reducing the latency of load operations. In various embodiments, logic of a processor accesses a prediction table after fetching instructions. For a prediction table hit, the logic executes a load instruction with a retrieved predicted address from the prediction table. For a prediction table miss, when the logic determines the address of the load instruction and hits in a learning table, the logic updates a level of confidence indication to indicate a higher level of confidence when a stored address matches the determined address. When the logic determines the level of confidence indication stored in a given table entry of the learning table meets a threshold, the logic allocates, in the prediction table, information stored in the given entry. Therefore, the predicted address is available during the next lookup of the prediction table.

    Hierarchical clock control using hysterisis and threshold management
    12.
    发明授权
    Hierarchical clock control using hysterisis and threshold management 有权
    使用滞后和阈值管理的分层时钟控制

    公开(公告)号:US09494997B2

    公开(公告)日:2016-11-15

    申请号:US14305514

    申请日:2014-06-16

    Applicant: Apple Inc.

    Abstract: In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved.

    Abstract translation: 在一些实施例中,系统可以包括子层次时钟控制。 在一些实施例中,系统可以包括主单元。 主单元可以包括电耦合到从单元的接口单元。 接口单元可以在使用期间由主单元监视从单元的使用请求。 在一些实施例中,接口单元可以在不使用期间关闭从单元的时钟。 在一些实施例中,接口单元可以确定在向从单元开启时钟之前是否经过预定时间段,使得关闭从单元导致系统实现更高的效率。 在一些实施例中,在使用期间,接口单元可以在不使用期间维持从单元的电力。 接口单元可以在不使用期间维持从单元的电力,从而保存存储在从单元中的数据。

    HIERARCHICAL CLOCK CONTROL USING HYSTERISIS AND THRESHOLD MANAGEMENT
    13.
    发明申请
    HIERARCHICAL CLOCK CONTROL USING HYSTERISIS AND THRESHOLD MANAGEMENT 有权
    使用滞后和阈值管理的分级时钟控制

    公开(公告)号:US20150362978A1

    公开(公告)日:2015-12-17

    申请号:US14305514

    申请日:2014-06-16

    Applicant: Apple Inc.

    Abstract: In some embodiments, a system may include a sub-hierarchy clock control. In some embodiments, the system may include a master unit. The master unit may include an interface unit electrically coupled to a slave unit. The interface unit may monitor, during use, usage requests of the slave unit by the master unit. In some embodiments, the interface unit may turn off clocks to the slave unit during periods of nonuse. In some embodiments, the interface unit may determine if a predetermined period of time elapses before turning on clocks to the slave unit such that turning off the slave unit resulted in the system achieving greater efficiency. In some embodiments, the interface unit may maintain, during use, power to the slave unit during periods of nonuse. The interface unit may maintain power to the slave unit during periods of nonuse such that data stored in the slave unit is preserved.

    Abstract translation: 在一些实施例中,系统可以包括子层次时钟控制。 在一些实施例中,系统可以包括主单元。 主单元可以包括电耦合到从单元的接口单元。 接口单元可以在使用期间由主单元监视从单元的使用请求。 在一些实施例中,接口单元可以在不使用期间关闭从单元的时钟。 在一些实施例中,接口单元可以确定在向从单元开启时钟之前是否经过预定时间段,使得关闭从单元导致系统实现更高的效率。 在一些实施例中,在使用期间,接口单元可以在不使用期间维持从单元的电力。 接口单元可以在不使用期间维持从单元的电力,从而保存存储在从单元中的数据。

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