公开(公告)号：US11651736B2

公开(公告)日：2023-05-16

申请号：US17680059

申请日：2022-02-24

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

CPC classification number: G09G3/3258 ,  H01L27/3262 ,  H01L29/7869 ,  G09G2300/0842 ,  G09G2320/0233 ,  G09G2320/043

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US11580905B2

公开(公告)日：2023-02-14

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US11532282B2

公开(公告)日：2022-12-20

申请号：US17501530

申请日：2021-10-14

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Zino Lee ,  Chun-Chieh Lin ,  Chen-Ming Chen

IPC: G09G3/3291 ,  G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.

公开(公告)号：US20220181418A1

公开(公告)日：2022-06-09

申请号：US17504230

申请日：2021-10-18

Applicant: Apple Inc.

Inventor： Jung Yen Huang ,  Shinya Ono ,  Chin-Wei Lin ,  Akira Matsudaira ,  Cheng Min Hu ,  Chih Pang Chang ,  Ching-Sang Chuang ,  Gihoon Choo ,  Jiun-Jye Chang ,  Po-Chun Yeh ,  Shih Chang Chang ,  Yu-Wen Liu ,  Zino Lee

IPC: H01L27/32 ,  H01L29/786 ,  H01L29/66

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.

公开(公告)号：US10916198B2

公开(公告)日：2021-02-09

申请号：US16716911

申请日：2019-12-17

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US20210020109A1

公开(公告)日：2021-01-21

申请号：US17062786

申请日：2020-10-05

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee ,  Yun Wang ,  Fan Gui

IPC: G09G3/3258 ,  H01L27/32 ,  H01L29/786

Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

公开(公告)号：US12014686B2

公开(公告)日：2024-06-18

申请号：US17970842

申请日：2022-10-21

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

IPC: G09G3/3266

CPC classification number: G09G3/3266 ,  G09G2300/0809 ,  G09G2300/0852 ,  G09G2320/0233

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.

公开(公告)号：US11922887B1

公开(公告)日：2024-03-05

申请号：US17368472

申请日：2021-07-06

Applicant: Apple Inc.

Inventor： Shinya Ono ,  Chin-Wei Lin ,  Chuan-Jung Lin ,  Gihoon Choo ,  Hassan Edrees ,  Hei Kam ,  Jung Yen Huang ,  Pei-En Chang ,  Rungrot Kitsomboonloha ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3275 ,  H10K59/121 ,  H10K59/126 ,  H10K59/131

CPC classification number: G09G3/3275 ,  H10K59/1213 ,  H10K59/1216 ,  H10K59/126 ,  H10K59/131 ,  G09G2320/0214

Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated thin-film transistors. The diode may be coupled to drive transistor circuitry, a data loading transistor, and emission transistors. The drive transistor circuitry may include at least two transistor portions connected in series. The data loading transistor has a drain region connected to a data line and a source region connected directly to the drive transistor circuitry. The data line may be connected to and overlap the drain region of the data loading transistor. The data line and the source region of the data loading transistor are non-overlapping to reduce row-to-row crosstalk.

公开(公告)号：US20230014107A1

公开(公告)日：2023-01-19

申请号：US17749045

申请日：2022-05-19

Applicant: Apple Inc.

Inventor： Rungrot Kitsomboonloha ,  Chin-Wei Lin ,  Shinya Ono ,  Gihoon Choo ,  Hao-Lin Chiu ,  Kyung Wook Kim ,  Pei-En Chang ,  Szu-Hsien Lee ,  Zino Lee

IPC: G09G3/3225

Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a logic sub-circuit and an output buffer sub-circuit. The output buffer sub-circuit may include depletion mode semiconducting oxide transistors with high mobility. The logic sub-circuit may include semiconducting oxide transistors, some of which can be depletion mode transistors and some of which can be enhancement mode transistors with lower mobility. The logic sub-circuit may include at least a carry circuit, a voltage setting circuit, an inverting circuit, a discharge circuit.

公开(公告)号：US20220284860A1

公开(公告)日：2022-09-08

申请号：US17317128

申请日：2021-05-11

Applicant: Apple Inc.

Inventor： Chin-Wei Lin ,  Shinya Ono ,  Zino Lee

IPC: G09G3/3266

Abstract: A display may include an array of pixels. Each pixel in the array may include a drive transistor, emission transistors, a data loading transistor, a gate voltage setting transistor, an initialization transistor, an anode reset transistor, a storage capacitor, and an optional current boosting capacitor. A data refresh may include a initialization phase, a threshold voltage sampling phase, and a data programming phase. The threshold voltage sampling phase can be substantially longer than the data programming phase to decrease a current sampling level during the threshold voltage sampling phase, which helps reduce the display luminance sensitivity to temperature variations.