公开(公告)号：US11663132B2

公开(公告)日：2023-05-30

申请号：US17500309

申请日：2021-10-13

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Jacob Martin Degasperis ,  Alexander Cole Shulyak

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/02 ,  G06F12/1027 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F12/0238 ,  G06F12/0811 ,  G06F12/1027

Abstract: A technique is provided for prefetching data items. An apparatus has a storage structure with a plurality of entries to store data items. The storage structure is responsive to access requests from processing circuitry to provide access to the data items. The apparatus has prefetch circuitry to prefetch data and correlation information storage to store correlation information for a plurality of data items. The correlation information identifies, for each of the plurality of data items, one or more correlated data items. The prefetch circuitry is configured to monitor the access requests from the processing circuitry. In response to detecting a hit in the correlation information storage for a particular access request that identifies a requested data item for which the correlation information storage stores correlation information, the prefetch circuitry is configured to prefetch the one or more correlated data items identified by the correlation information for the requested data item.

公开(公告)号：US11625349B1

公开(公告)日：2023-04-11

申请号：US17529768

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joshua Randall ,  Alexander Cole Shulyak ,  Jose Alberto Joao

IPC: G06F9/38 ,  G06F13/36

Abstract: An apparatus and method are provided for managing prefetch transactions. The apparatus has an interconnect for providing communication paths between elements coupled to the interconnect. The elements coupled to the interconnect comprise at least a requester element to initiate transactions, and a plurality of completer elements each of which is arranged to respond to a transaction received by that completer element. Congestion tracking circuitry maintains, in association with the requester element, a congestion indication for each of a plurality of routes through the interconnect used to propagate transactions initiated by that requester element. Each route comprises one or more communication paths, and the route employed to propagate a given transaction is dependent on a target completer element for that transaction. Prefetch throttling circuitry then identifies, in response to an indication of a given prefetch transaction that the requester element wishes to initiate, the target completer element amongst the plurality of completer elements to which that given prefetch transaction would be issued. It then determines whether to issue the given prefetch transaction in dependence on the congestion indication for the route that has been determined.

公开(公告)号：US11442863B2

公开(公告)日：2022-09-13

申请号：US17093792

申请日：2020-11-10

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Adrian Montero ,  Joseph Michael Pusdesris ,  Karthik Sundaram ,  Yasuo Ishii

IPC: G06F12/0862

Abstract: Data processing apparatuses and methods of processing data are disclosed. The operations comprise: storing copies of data items; and storing, in a producer pattern history table, a plurality of producer-consumer relationships, each defining an association between producer load indicator and a plurality of consumer load entries, each consumer load entry comprising a consumer load indicator and one or more usefulness metrics. Further steps comprise: initiating, in response to a data load from an address corresponding to the producer load indicator in the producer pattern history table and when at least one of the corresponding one or more usefulness meets a criterion, a producer prefetch of data to be prefetched for storing as a local copy; and issuing, when the data is returned, one or more consumer prefetches to return consumer data from a consumer address generated from the data returned by the producer prefetch and a consumer load indicator of a consumer load entry.

公开(公告)号：US12229556B2

公开(公告)日：2025-02-18

申请号：US18353345

申请日：2023-07-17

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Yasuo Ishii ,  Joseph Michael Pusdesris

IPC: G06F9/30 ,  G06F13/16

Abstract: Processing circuitry to execute load operations, each associated with an identifier. Prediction circuitry to receive a given load value associated with a given identifier, and to make, in dependence on the given load value, a prediction indicating a predicted load value for a subsequent load operation to be executed by the processing circuitry and an ID-delta value indicating a difference between the given identifier and an identifier of the subsequent load operation. The predicted load value being predicted in dependence on at least one occurrence of each of the given load value and the predicted load value during execution of a previously-executed sequence of load operations. The prediction circuitry is configured to determine the ID-delta value in dependence on a difference between identifiers associated with the at least one occurrence of each of the given load value and the predicted load value in the previously-executed sequence of load operations.

公开(公告)号：US11782845B2

公开(公告)日：2023-10-10

申请号：US17541007

申请日：2021-12-02

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Joseph Michael Pusdesris ,  Abhishek Raja ,  Karthik Sundaram ,  Anoop Ramachandra Iyer ,  Michael Brian Schinzler ,  James David Dundas ,  Yasuo Ishii

IPC: G06F12/1027

CPC classification number: G06F12/1027

Abstract: An apparatus comprises memory management circuitry to perform a translation table walk for a target address of a memory access request and to signal a fault in response to the translation table walk identifying a fault condition for the target address, prefetch circuitry to generate a prefetch request to request prefetching of information associated with a prefetch target address to a cache; and faulting address prediction circuitry to predict whether the memory management circuitry would identify the fault condition for the prefetch target address if the translation table walk was performed by the memory management circuitry for the prefetch target address. In response to a prediction that the fault condition would be identified for the prefetch target address, the prefetch circuitry suppresses the prefetch request and the memory management circuitry prevents the translation table walk being performed for the prefetch target address of the prefetch request.

公开(公告)号：US11775440B2

公开(公告)日：2023-10-03

申请号：US17579842

申请日：2022-01-20

Applicant: Arm Limited

Inventor： Alexander Cole Shulyak ,  Balaji Vijayan ,  Karthik Sundaram ,  Yasuo Ishii ,  Joseph Michael Pusdesris

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/602

Abstract: Indirect prefetch circuitry initiates a producer prefetch requesting return of producer data having a producer address and at least one consumer prefetch to request prefetching of consumer data having a consumer address derived from the producer data. A producer prefetch filter table stores producer filter entries indicative of previous producer addresses of previous producer prefetches. Initiation of a requested producer prefetch for producer data having a requested producer address is suppressed when a lookup of the producer prefetch filter table determines that the requested producer address hits against a producer filter entry of the table. The lookup of the producer prefetch filter table for the requested producer address depends on a subset of bits of the requested producer address including at least one bit which distinguishes different chunks of data within a same cache line.

公开(公告)号：US11416404B2

公开(公告)日：2022-08-16

申请号：US16743399

申请日：2020-01-15

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Alexander Cole Shulyak

IPC: G06F12/00 ,  G06F12/0862 ,  G06F9/50 ,  G06F12/14

Abstract: There is provided a data processing apparatus comprising table circuitry to store a table that indicates, for a program counter value of an instruction that performs a memory access operation at a memory address, one or more offsets of the memory address and an associated confidence for each of the one or more offsets. Prefetch circuitry prefetches data based on each of the offsets in dependence on the associated confidence. Each of the offsets of the memory address is dynamically determined.

公开(公告)号：US20210216461A1

公开(公告)日：2021-07-15

申请号：US16743399

申请日：2020-01-15

Applicant: Arm Limited

Inventor： Joseph Michael Pusdesris ,  Alexander Cole Shulyak

IPC: G06F12/0862 ,  G06F12/14 ,  G06F9/50

Abstract: There is provided a data processing apparatus comprising table circuitry to store a table that indicates, for a program counter value of an instruction that performs a memory access operation at a memory address, one or more offsets of the memory address and an associated confidence for each of the one or more offsets. Prefetch circuitry prefetches data based on each of the offsets in dependence on the associated confidence. Each of the offsets of the memory address is dynamically determined.