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    Apparatus and method for estimating a shift amount when performing floating-point subtraction
    11.
    发明授权
    Apparatus and method for estimating a shift amount when performing floating-point subtraction 有权

    公开(公告)号：US10140093B2

    公开(公告)日：2018-11-27

    申请号：US15473841

    申请日：2017-03-30

    Applicant: ARM Limited

    Inventor： David Raymond Lutz ,  Ian Michael Caulfield

    IPC: G06F7/485 ,  G06F5/01

    Abstract: An apparatus and method are provided for estimating a shift amount when employing processing circuitry to perform a subtraction operation to subtract a second significand value of a second floating-point operand from a first significand value of a first floating-point operand in order to generate a difference value. Shift estimation circuitry then determines an estimated shift amount to be applied to the difference value. The shift estimation circuitry comprises significand analysis circuitry to generate, from analysis of the significand values of the two floating-point operands, a first bit string identifying a most significant bit position within the difference value that is predicted to have its bit set to a determined value. In parallel, shift limiting circuitry generates from an exponent value a second bit string identifying a shift limit bit position. The shift limiting circuitry has computation circuitry to perform, for each bit position in at least a subset of bit positions of the second bit string, an associated computation using bits of the exponent value to determine a value for that bit position within the second bit string. The associated computation is different for different bit positions. Combining circuitry then generates a combined bit string from the first and second bit strings, and shift determination circuitry determines the estimated shift amount from the combined bit string.

    Overlap propagation operation
    12.
    发明授权
    Overlap propagation operation 有权

    公开(公告)号：US09928031B2

    公开(公告)日：2018-03-27

    申请号：US14939301

    申请日：2015-11-12

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz ,  Christopher Neal Hinds

    IPC: G06F7/483 ,  G06F7/50

    CPC classification number: G06F7/483 ,  G06F7/50 ,  G06F2207/4924

    Abstract: Processing circuitry is provided to perform an overlap propagating operation on a first data value to generate a second data value, the first and second data values having a redundant representation representing a P-bit numeric value using an M-bit data value comprising a plurality of N-bit portions, where M>P>N. In the redundant representation, each N-bit portion other than a most significant N-bit portion includes a plurality of overlap bits having a same significance as a plurality of least significant bits of a following N-bit portion. Each N-bit portion of the second data value other than a least significant N-bit portion is generated by adding non-overlap bits of a corresponding N-bit portion of the first data value to the overlap bits of a preceding N-bit portion of the first data value. This provides a faster technique for reducing the chance of overflow during addition of the redundantly represented M-bit value.

    Standalone floating-point conversion unit
    15.
    发明授权
    Standalone floating-point conversion unit 有权
    独立浮点转换单元

    公开(公告)号：US09582248B2

    公开(公告)日：2017-02-28

    申请号：US14498172

    申请日：2014-09-26

    Applicant: ARM Limited

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G06F5/01 ,  G06F7/485

    CPC classification number: G06F7/485

    Abstract: A data processing apparatus includes floating-point adder circuitry and floating-point conversion circuitry that generates a floating-point number as an output by performing a conversion on any input having a format from a list of formats including: an integer number, a fixed-point number, and a floating-point number having a format smaller than the output floating-point number. The floating-point conversion circuitry is physically distinct from the floating-point adder circuitry.

    Abstract translation: 数据处理装置包括浮点加法器电路和浮点转换电路，其通过对从格式列表格式的任何输入执行转换来产生浮点数，该格式包括：整数， 点数，以及格式小于输出浮点数的浮点数。 浮点转换电路在物理上不同于浮点加法器电路。

    Predicting saturation in a shift operation
    16.
    发明授权
    Predicting saturation in a shift operation 有权
    预测换档操作中的饱和度

    公开(公告)号：US09564187B2

    公开(公告)日：2017-02-07

    申请号：US14933402

    申请日：2015-11-05

    Applicant: ARM Limited

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G11C7/00 ,  G11C7/10 ,  G06F5/01 ,  G06F9/30 ,  G06F7/499

    CPC classification number: G11C7/1078 ,  G06F5/01 ,  G06F7/49921 ,  G06F9/30018 ,  G06F9/30032 ,  G11C7/1084

    Abstract: Apparatus for data processing and a method of data processing are provided. Shift circuitry performs a shift operation in response to a shift instruction, shifting bits of an input data value in a direction specified by the shift instruction. Bit location indicator generation circuitry and comparison circuitry operate in parallel with the shift circuitry. The bit location indicator indicates at least one bit location in the input data value which must not have a bit set if the shifted data value is not to saturate. Comparison circuitry compares the bit location indicator with the input data value and indicates a saturation condition if any bits are indicated by the bit position indicator for bit locations which hold set bits in the input data value. A faster indication of the saturation condition thus results.

    Abstract translation: 提供了数据处理装置和数据处理方法。 移位电路响应于移位指令执行移位操作，在由移位指令指定的方向上移位输入数据值的位。 位位置指示符生成电路和比较电路与移位电路并行操作。 位位置指示符指示输入数据值中的至少一个位位置，如果移位的数据值不饱和，则该位置不能有位置位。 比较电路将位位置指示符与输入数据值进行比较，并且如果位位置指示符指示了用于保持输入数据值中的设置位的位位置的任何位，则表示饱和条件。 因此，更快地显示饱和条件。

    Tininess detection
    17.
    发明授权
    Tininess detection 有权

    公开(公告)号：US12164881B2

    公开(公告)日：2024-12-10

    申请号：US17384001

    申请日：2021-07-23

    Applicant: Arm Limited

    Inventor： David Raymond Lutz ,  David M. Russinoff ,  Harsha Valsaraju

    IPC: G06F7/483 ,  G06F5/01 ,  G06F7/10 ,  G06F7/499

    Abstract: An apparatus comprises floating-point processing circuitry to perform a floating-point operation with rounding to generate a floating-point result value; and tininess detection circuitry to detect a tininess status indicating whether an outcome of the floating-point operation is tiny. A tiny outcome corresponds to a non-zero number with a magnitude smaller than a minimum non-zero magnitude representable as a normal floating-point number in a floating-point format to be used for the floating-point result value. The tininess detection circuitry comprises hardware circuit logic configured to support both before rounding tininess detection and after rounding tininess detection for detecting the tininess status.

    Floating-point scaling operation
    18.
    发明授权
    Floating-point scaling operation 有权

    公开(公告)号：US11347511B2

    公开(公告)日：2022-05-31

    申请号：US16416453

    申请日：2019-05-20

    Applicant: Arm Limited

    Inventor： David Raymond Lutz

    IPC: G06F9/30

    Abstract: An apparatus has floating-point multiplying circuitry to perform a floating-point multiply operation to multiply first and second floating-point operands to generate a product floating-point value. Shared hardware circuitry of the floating-point multiplying circuitry is reused to also support a floating-point scaling instruction specifying an input floating-point operand and an integer operand, which causes a floating-point scaling operation to be performed to generate an output floating-point value corresponding to a product of the input floating-point operand and a scaling factor 2X, where X is an integer represented by the integer operand.

    HIGH-PRECISION ANCHORED-IMPLICIT PROCESSING
    19.
    发明申请
    HIGH-PRECISION ANCHORED-IMPLICIT PROCESSING 有权

    公开(公告)号：US20220129245A1

    公开(公告)日：2022-04-28

    申请号：US17081068

    申请日：2020-10-27

    Applicant: Arm Limited

    Inventor： Neil Burgess ,  Christopher Neal Hinds ,  David Raymond Lutz ,  Pedro Olsen Ferreira

    IPC: G06F7/499 ,  G06F7/487 ,  G06F9/38

    Abstract: An apparatus includes a processing circuit and a storage device. The processing circuit is configured to perform one or more processing operations in response to one or more instructions to generate an anchored-data element. The storage device is configured to store the anchored-data element. A format of the anchored-data element includes an identification item, an overlap item, and a data item. The data item is configured to hold a data value of the anchored-data element. The identification item indicates an anchor value for the data value or one or more special values.

    Alignment shifting and incrementing to determine a rounded result of adding first and second floating-point operands
    20.
    发明授权
    Alignment shifting and incrementing to determine a rounded result of adding first and second floating-point operands 有权

    公开(公告)号：US11119729B2

    公开(公告)日：2021-09-14

    申请号：US16367672

    申请日：2019-03-28

    Applicant: Arm Limited

    Inventor： David Raymond Lutz

    IPC: G06F7/485 ,  G06F7/499

    Abstract: A floating-point adding circuitry is provided to add first and second floating-point operands each comprising a significand and an exponent. Alignment shift circuitry shifts a smaller-operand significand to align with a larger-operand significand, based on an exponent difference. Incrementing circuitry generates alternative versions of the larger-operand significand, each version based on a different rounding increment applied to the larger-operand significand. A number of candidate sum values are generated by adding circuits, each candidate sum value representing a sum of the shifted smaller-operand significand and a respective one of the alternative versions of the larger-operand significand. One of the candidate sum values is selected as a rounded result of adding the first and second floating-point operands. This allows floating-point addition to be performed faster as the latency of the rounding increment can be hidden in the shadow of the latency of the alignment shift.

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