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公开(公告)号：US20190303161A1
公开(公告)日：2019-10-03
申请号：US15939827
申请日：2018-03-29
申请人： Arm Limited
摘要： An apparatus and method are provided for controlling branch prediction. The apparatus has processing circuitry for executing instructions, and branch prediction circuitry that comprises a plurality of branch prediction mechanisms used to predict target addresses for branch instructions to be executed by the processing circuitry. The branch instructions comprise a plurality of branch types, where one branch type is a return instruction. The branch prediction mechanisms include a return prediction mechanism used by default to predict a target address when a return instruction is detected by the branch prediction circuitry. However, the branch prediction circuitry is responsive to a trigger condition indicative of misprediction of the target address when using the return prediction mechanism to predict the target address for a given return instruction, to switch to using an alternative branch prediction mechanism for predicting the target address for the given return instruction. This has been found to improve performance in certain situations.
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公开(公告)号：US20230418611A1
公开(公告)日：2023-12-28
申请号：US17847378
申请日：2022-06-23
申请人： Arm Limited
CPC分类号： G06F9/30145 , G06F9/30065 , G06F9/3844 , G06F9/3802
摘要： Prediction circuitry predicts a number of iterations of a fetching process to be performed to control fetching of data/instructions for processing operations that are predicted to be performed by processing circuitry. The processing circuitry can tolerate performing unnecessary iterations of the fetching process following an over-prediction of the number of iterations. In response to the processing circuitry resolving an actual number of iterations, the prediction circuitry adjusts the prediction state information used to predict the number of iterations, based on whether a first predicted number of iterations, predicted based on a first iteration prediction parameter, provides a good prediction (when the first predicted number of iterations is in a range i_cnt to i_cnt+N, where i_cnt is the actual number of iterations and N≥1), or a misprediction (when the first predicted number of iterations is outside the range i_cnt to i_cnt+N).
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公开(公告)号：US20230409325A1
公开(公告)日：2023-12-21
申请号：US17838713
申请日：2022-06-13
申请人： Arm Limited
CPC分类号： G06F9/30145 , G06F9/30189 , G06F9/325 , G06F9/3867
摘要： Processing circuitry performs processing operations in response to micro-operations. Front end circuitry supplies the micro-operations to be processed by the processing circuitry. Prediction circuitry generates a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry. The front end circuitry varies, based on a level of confidence in the prediction of the number of loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry.
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公开(公告)号：US20230195467A1
公开(公告)日：2023-06-22
申请号：US17556166
申请日：2021-12-20
申请人： Arm Limited
CPC分类号： G06F9/3844 , G06F9/3816 , G06F9/30054
摘要： A data processing apparatus is provided that includes bimodal control flow prediction circuitry for performing a prediction of whether a conditional control flow instruction will be taken. Storage circuitry stores, in association with the control flow instruction, a stored state of the data processing apparatus and reversal circuitry reverses the prediction in dependence on the stored state of the data processing apparatus corresponding with a current state of the data processing apparatus when execution of the control flow instruction is to be performed.
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公开(公告)号：US20200081717A1
公开(公告)日：2020-03-12
申请号：US16541507
申请日：2019-08-15
申请人： Arm Limited
IPC分类号： G06F9/38
摘要： Branch prediction circuitry comprises: a return address prediction structure to store at least one predicted return address; and a branch target buffer (BTB) structure comprising entries each for specifying predicted branch information for a corresponding block of instructions. Within at least a subset of entries of the BTB structure, each entry specifies the predicted branch information with an encoding incapable of simultaneously indicating both: that the corresponding block of instructions is predicted to include a return branch instruction (for which the return address prediction structure is used to predict the target address); and the predicted target address for the return branch instruction. This can provide a more efficient BTB structure which requires less circuit area and power for a given level of branch prediction performance.
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公开(公告)号：US20200065105A1
公开(公告)日：2020-02-27
申请号：US16108115
申请日：2018-08-22
申请人： Arm Limited
IPC分类号： G06F9/38
摘要： An apparatus and method are provided for detecting regularity in a number of occurrences of an event observed during multiple instances of a counting period. The apparatus has regularity detection circuitry for seeking to detect such a regularity, and a storage providing a storage entry having a count value field to store a count value and a confidence indication field to indicate a confidence in the regularity. The regularity detection circuitry is arranged to consider the multiple instances of the counting period in pairs, for one instance in the pair the regularity detection circuitry incrementing the count value following each occurrence of the event, and for the other instance in the pair the regularity detection circuitry decrementing the count value following each occurrence of the event. Check circuitry is then arranged, following completion of both counting periods in the pair, to adjust the confidence indication to indicate an increased confidence when it is determined that the count value has returned to an initial value, and otherwise to adjust the confidence indication to indicate a decreased confidence and to reset the count value to the initial value. Such an approach provides a particularly storage efficient mechanism for seeking to detect regularity in a number of occurrences of an event.
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公开(公告)号：US20200050458A1
公开(公告)日：2020-02-13
申请号：US16100344
申请日：2018-08-10
申请人： Arm Limited
摘要： An apparatus and method are provided for performing branch prediction. The apparatus has processing circuitry to execute instructions, and branch prediction circuitry for making branch outcome predictions in respect of branch instructions. The branch prediction circuitry includes loop minimum iteration prediction circuitry having one or more entries, where each entry is associated with a loop controlling branch instruction that controls repeated execution of a loop comprising a number of instructions. During a training phase for an entry, the loop minimum iteration prediction circuitry seeks to identify a minimum number of iterations of the loop. The loop minimum iteration prediction circuitry is then arranged, when the training phase has successfully identified a minimum number of iterations, to subsequently identify a branch outcome prediction for the associated loop controlling branch instruction for use during the minimum number of iterations. It has been found that such an approach can significantly improve prediction accuracy for loop controlling branch instructions associated with loops that do not have a stable total number of iterations.
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公开(公告)号：US20190196833A1
公开(公告)日：2019-06-27
申请号：US15852065
申请日：2017-12-22
申请人： Arm Limited
摘要： Data processing circuitry comprises fetch circuitry to fetch blocks, containing instructions for execution, defined by a fetch queue; and prediction circuitry to predict one or more next blocks to be fetched and to add the predicted next blocks to the fetch queue; the prediction circuitry comprising: branch prediction circuitry to detect a predicted branch destination for a branch instruction in a current block, the predicted branch destination representing either a branch target for a branch predicted to be taken or a next instruction after the branch instruction, for a branch predicted not to be taken; and sequence prediction circuitry to detect sequence data, associated with the predicted branch destination, identifying a next block following the predicted branch destination in the program flow order having a next instance of a branch instruction, to add to the fetch queue the identified next block and any intervening blocks between the current block and the identified next block, and to initiate branch prediction in respect of the predicted next instance of a branch instruction.
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公开(公告)号：US20230195468A1
公开(公告)日：2023-06-22
申请号：US17557583
申请日：2021-12-21
申请人： Arm Limited
发明人： Houdhaifa BOUZGUARROU , Guillaume BOLBENES , Thibaut Elie LANOIS , Vincenzo CONSALES , Chang Joo LEE
CPC分类号： G06F9/3806 , G06F9/3844 , G06F9/3005
摘要： An apparatus has a fetch queue to identify a sequence of instructions to be fetched for execution and prediction circuitry to predict upcoming control flow and to control which instructions are identified in the fetch queue in dependence on the prediction. The prediction circuitry predicts multi-taken sequences which are sequences of instructions in which control flow is diverted by a first control flow changing instruction to a series of instructions terminating in a second control flow changing instruction that diverts control flow to a target address. The apparatus also has prediction confidence calculation circuitry to calculate confidence levels for respective multi-taken sequences. Each confidence level is indicative of a confidence in an accuracy of prediction of its respective multi-taken sequence. When the confidence level for a particular multi-taken sequence satisfies a prediction confidence condition, the prediction confidence tracking circuitry allows the particular multi-taken sequence to be predicted by the prediction circuitry. The prediction circuitry causes the series of instructions and the target instruction for the particular multi-taken sequence to be identified in the fetch queue when the prediction circuitry predicts the particular multi-taken sequence and further predictions to be made starting from the target address for the particular multi-taken sequence.
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公开(公告)号：US20230118268A1
公开(公告)日：2023-04-20
申请号：US17501257
申请日：2021-10-14
申请人： Arm Limited
摘要： Aspects of the present disclosure relate to an apparatus comprising prediction circuitry having a plurality of hierarchical prediction units to perform respective hierarchical predictions of instructions for execution, wherein predictions higher in the hierarchy have a higher expected accuracy than predictions lower in the hierarchy. Responsive to a given prediction higher in the hierarchy being different to a corresponding prediction lower in the hierarchy, the corresponding prediction lower in the hierarchy is corrected. A prediction correction metric determination unit determines a prediction correction metric indicative of an incidence of uncorrected predictions performed by the prediction circuitry. Fetch circuitry fetches instructions predicted by at least one of said plurality of hierarchical predictions, and delays said fetching based on the prediction correction metric indicating an incidence of uncorrected predictions below a threshold.
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