公开(公告)号：US20250053421A1

公开(公告)日：2025-02-13

申请号：US18448240

申请日：2023-08-11

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Albin Pierrick TONNERRE ,  Geoffray Matthieu LACOURBA

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus comprises at least one register rename table structure comprising rename entries for indicating register mappings between architectural registers and corresponding physical registers, and register rename circuitry to update the register mappings indicated by the rename entries. Rename entries corresponding to at least one set of architectural registers support a cleared-register encoding. In response to an operation specifying a source architectural register for which a corresponding rename entry is set to the cleared-register encoding, the register rename circuitry controls the processing circuitry to process that operation with a source operand corresponding to the source architectural register being treated as having a predetermined value. In response to detection of a register clearing event indicating that at least one set of architectural registers is to be treated as having been cleared to the predetermined value, the register rename circuitry sets rename entries corresponding to the at least one set of architectural registers to the cleared-register encoding.

公开(公告)号：US20250004769A1

公开(公告)日：2025-01-02

申请号：US18343294

申请日：2023-06-28

Applicant: Arm Limited

Inventor： Quentin Éric NOUVEL ,  Luca NASSI ,  Nicola PIANO ,  Albin Pierrick TONNERRE ,  Geoffray Matthieu LACOURBA

IPC: G06F9/30

Abstract: There is provided an apparatus, method for data processing. The apparatus comprises post decode cracking circuitry responsive to receipt of decoded instructions from decode circuitry of a processing pipeline, to crack the decoded instructions into micro-operations to be processed by processing circuitry of the processing pipeline. The post decode cracking circuitry is responsive to receipt of a decoded instruction suitable for cracking into a plurality of micro-operations including at least one pair of micro-operations having a producer-consumer data dependency, to generate the plurality of micro-operations including a producer micro-operation and a consumer micro-operation, and to assign a transfer register to transfer data between the producer micro-operation and the consumer micro-operation.

公开(公告)号：US20230409325A1

公开(公告)日：2023-12-21

申请号：US17838713

申请日：2022-06-13

Applicant: Arm Limited

Inventor： Guillaume BOLBENES ,  Thibaut Elie LANOIS ,  Houdhaifa BOUZGUARROU ,  Luca NASSI

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/32

CPC classification number: G06F9/30145 ,  G06F9/30189 ,  G06F9/325 ,  G06F9/3867

Abstract: Processing circuitry performs processing operations in response to micro-operations. Front end circuitry supplies the micro-operations to be processed by the processing circuitry. Prediction circuitry generates a prediction of a number of loop iterations for which one or more micro-operations per loop iteration are to be supplied by the front end circuitry, where an actual number of loop iterations to be processed by the processing circuitry is resolvable by the processing circuitry based on at least one operand corresponding to a first loop iteration to be processed by the processing circuitry. The front end circuitry varies, based on a level of confidence in the prediction of the number of loop iterations, a supply rate with which the one or more micro-operations for at least a subset of the loop iterations are supplied to the processing circuitry.

公开(公告)号：US20230244606A1

公开(公告)日：2023-08-03

申请号：US17592022

申请日：2022-02-03

Applicant: Arm Limited

Inventor： Geoffray LACOURBA ,  Luca NASSI ,  Damien CATHRINE ,  Stefano GHIGGINI ,  Albin Pierrick TONNERRE

IPC: G06F12/0862

CPC classification number: G06F12/0862 ,  G06F2212/602

Abstract: Circuitry comprises a memory system to store data items; cache memory storage to store a copy of one or more data items, the cache memory storage comprising a hierarchy of two or more cache levels; detector circuitry to detect at least a property of data items for storage by the cache memory storage; and control circuitry to control eviction, from a given cache level, of a data item stored by the given cache level, the control circuitry being configured to select a destination to store a data item evicted from the given cache level in response to a detection by the detector circuitry.

公开(公告)号：US20190361705A1

公开(公告)日：2019-11-28

申请号：US15987002

申请日：2018-05-23

Applicant: Arm Limited

Inventor： Luca NASSI ,  Cédric Denis Robert AIRAUD ,  Rémi Marius TEYSSIER ,  Albin Pierrick TONNERRE

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are provided for storing source operands for operations. The apparatus comprises execution circuitry for performing operations on data values, and a register file comprising a plurality of registers to store the data values operated on by the execution circuitry. Issue circuitry is also provided that has a pending operations storage identifying pending operations awaiting performance by the execution circuitry and selection circuitry to select pending operations from the pending operation storage to issue to the execution circuitry. The pending operations storage comprises an entry for each pending operation, each entry storing attribute information identifying the operation to be performed, where that attribute information includes a source identifier field for each source operand of the pending operation. The source identifier field has a field size sufficient to enable a register identifier to be stored within the source identifier field to identify the register used to store the data value forming the source operand. However, the field size is insufficient to store the data value as stored in the register. Value analysis circuitry is responsive to the execution circuitry generating a data value that will be used as a source operand for a pending operation, to determine whether a reduced size representation of that generated data value can be accommodated within the associated source identifier field of the entry for that pending operation. If so, the reduced size representation is generated and a control signal is issued to the issue circuitry to cause the register identifier for that source operand to be replaced by the reduced size representation of the data value. By such an approach, it is possible to increase the performance of the apparatus and/or to simplify the construction of the register file.