Abstract:
A Fringe-Field Switching (FFS) mode liquid crystal display (LCD) panel with optimized designs of pixel areas and/or liquid crystal materials is provided. The FFS mode LCD panel includes an active-element array substrate with a plurality of pixel areas, an opposite substrate, and a liquid crystal layer. Each pixel area comprises a plurality of first common electrodes, a second common electrode between the pixel area and another horizontally adjacent pixel area, and a pixel electrode. The optical transmittance and homogeneity of the pixel area of the display panel are modified by manipulating the relative position of the electrodes in the pixel areas on the active-element array substrate and/or adopting specific parameters of liquid crystal materials in the liquid crystal layer of the display panel.
Abstract:
A pixel unit includes a first pixel, a second pixel, a third pixel, a fourth pixel and a light-shielding structure. The first pixel has a plurality of first sub-pixels, the second pixel has a plurality of second sub-pixels, the third pixel has a plurality of third pixels, and the fourth pixel has a plurality of fourth sub-pixels. The first sub-pixel has a first electrode extending along a first tilting direction. The second sub-pixel has a second electrode extending along a second tilting direction. The third sub-pixel has a third electrode extending along a third tilting direction. The fourth sub-pixel has a fourth electrode extending along a fourth tilting direction. The first pixel, the second pixel, the third pixel and the fourth pixel surround the light-shielding structure collectively. The first tilting direction, the second tilting direction, the third tilting direction and the fourth tilting direction are different from each other.
Abstract:
A pixel unit includes a first pixel, a second pixel, a third pixel, a fourth pixel and a light-shielding structure. The first pixel has a plurality of first sub-pixels, the second pixel has a plurality of second sub-pixels, the third pixel has a plurality of third pixels, and the fourth pixel has a plurality of fourth sub-pixels. The first sub-pixel has a first electrode extending along a first tilting direction. The second sub-pixel has a second electrode extending along a second tilting direction. The third sub-pixel has a third electrode extending along a third tilting direction. The fourth sub-pixel has a fourth electrode extending along a fourth tilting direction. The first pixel, the second pixel, the third pixel and the fourth pixel surround the light-shielding structure collectively. The first tilting direction, the second tilting direction, the third tilting direction and the fourth tilting direction are different from each other.
Abstract:
An array substrate includes a scan line, a data line, a thin film transistor, a first transparent electrode, a passivation layer, and a second transparent electrode. The scan line and the data line interlace to define a pixel region. The gate dielectric layer of the thin film transistor overlaps the scan line and the data line and extends to cover the pixel region. The gate dielectric layer has a first region, a second region, and a third region. The first region corresponds to the semiconductor layer of the thin film transistor. The second region connects the first region and the third region. The thickness of the second region is different from that of the third region. The first transparent electrode covers the gate dielectric layer in the pixel region. The passivation layer covers the thin film transistor and the first transparent electrode. The second transparent electrode covers the passivation layer.
Abstract:
A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
Abstract:
A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.
Abstract:
A display device including a display area and a non-display area is provided. The display area includes a display panel, a switch unit and a first reflective film. The non-display area includes a second reflective film. The switch unit is disposed on the display panel. The first reflective film is disposed between the display panel and the switch unit. When the display device is set in a pattern mode, the display panel does not emit image light. For the pattern mode, the reflectivity in the display area is approximately equal to the reflectivity in the non-display area for ambient light.
Abstract:
A liquid crystal display panel includes a first substrate, a second substrate, a third substrate, a pixel electrode layer, a first common electrode layer, a first control electrode layer, a first liquid crystal layer, a second common electrode layer, a second control electrode layer and a second liquid crystal layer. The second substrate is opposite to the first substrate. The third substrate is opposite to the second substrate. The pixel electrode layer and the first common electrode layer are disposed on the first substrate. The first control electrode layer is disposed on the second substrate. The first liquid crystal layer is disposed between the first substrate and the second substrate. The second common electrode layer is disposed on the second substrate. The second control electrode layer is disposed on the third substrate. The second liquid crystal layer is disposed between the second substrate and the third substrate.
Abstract:
A pixel structure including a scan line, a data line, an active device, a pixel electrode, a capacitor electrode line, a semi-conductive pattern layer and at least one dielectric layer is provided. The active device is electrically connected to the scan line and the data line. The pixel electrode is electrically connected to the active device. The capacitor electrode line is located under the pixel electrode. A first storage capacitor is formed between the capacitor electrode line and the pixel electrode. The semi-conductive pattern layer is disposed between the capacitor electrode line and the pixel electrode, the pixel electrode is electrically connected to the semi-conductive pattern layer. A second storage capacitor is formed between the semi-conductive pattern layer and the capacitor electrode line. The dielectric layer is disposed between the capacitor electrode line and the pixel electrode and located between the semi-conductive pattern layer and the capacitor electrode line.