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公开(公告)号：US20240404591A1
公开(公告)日：2024-12-05
申请号：US18800530
申请日：2024-08-12
Inventor： Jason F. Ross
Abstract: A multi-bit, asynchronous e-fuse macro, the macro comprising: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with the e-fuse macro.
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Patent Agency Ranking
公开(公告)号：US20230197149A1
公开(公告)日：2023-06-22
申请号：US17552844
申请日：2021-12-16
Inventor： Jason F. Ross
CPC classification number: G11C11/5692 , G11C17/16 , G11C17/18
Abstract: A multi-bit, asynchronous e-fuse macro, the macro comprising: the following inputs: an input output enable, a power on reset, a write address, an input write enable, a ground clamp enable, and a write clock; a plurality of e-fuse bits; a supply voltage configured to allow programming at least one of the e-fuse bits; at least one fuse output; and self-timing and control circuitry configured to perform signaling, wherein each of the inputs is in electrical communication with said e-fuse macro.
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公开(公告)号：US20220392848A1
公开(公告)日：2022-12-08
申请号：US17340807
申请日：2021-06-07
Inventor： Jason F. Ross , Dale A. Rickard
IPC: H01L23/552 , G06F30/398
Abstract: An integrated circuit (IC) that is otherwise radiation tolerant implements a radiation tolerance limiting feature (RTLF) to ensure that the IC, as manufactured, will fail applicable radiation tolerance tests, thereby allowing it to be manufactured by any suitable IC foundry. Embodiments further include a programmable radiation tolerance feature (PRT) that can be actuated at an authorized actuation site after IC manufacture to override the RTLF, thereby rendering the IC radiation tolerant. The PRT and/or RTLF can include redundancy to ensure reliability. The PRT and/or RTLF can be obfuscated, encrypted, and/or password protected. Actuating the PRT can include applying a programming signal to the IC and/or uploading code to a programmable element after IC manufacture. A plurality of RTLFs can be included to ensure failure of any desired combination of applicable radiation tolerance tests, such as total radiation dosage, linear energy transfer events, radiation dose rate, and single event upset.
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公开(公告)号：US11342915B1
公开(公告)日：2022-05-24
申请号：US17173870
申请日：2021-02-11
Inventor： Jason F. Ross
IPC: H03K19/00 , H03K19/0175 , H03K19/0185
Abstract: A level shifting circuit, the circuit comprising a VL input; an I/O VL; a VCC input; an I/O VCC; a first pull-up resistor disposed between the VL input and I/O VL; a second pull-up resistor disposed between the VCC input and I/O VCC; a first pull-up assist circuit comprising a first pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VL and I/O VL; a second pull-up assist circuit comprising a second pull-up assist p-channel MOSFET having a source/body, drain, and gate, the source/body and drain being connected to VCC and I/O VCC, respectively; a pass-gate n-channel MOSFET in operative communication with I/O VL, I/O VCC, and VL, the pass-gate being configured to reduce the voltage level of a signal driven from I/O VCC to the voltage level of I/O VL; and a one-shot circuit configured to detect a I/O VL or I/O VCC transition from a low state to a high state, to produce a pulse in response thereto, and to communicate that pulse to the gates of the first and second pull-up assist p-channel MOSFETs, wherein the second pull-up resistor is configured to increase the voltage level of a signal driven from I/O VL to the voltage level of I/O VCC.
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15.发明申请公开(公告)号：US20200051961A1
公开(公告)日：2020-02-13
申请号：US16057204
申请日：2018-08-07
Inventor： Dale A. Rickard , Jason F. Ross , John T. Matta , Richard J. Ferguson , Alan F. Dennis , Joseph R. Marshall, JR. , Daniel L. Stanley
IPC: H01L25/16 , H01L23/498 , H01L23/00 , H01L27/112 , H01L25/00
Abstract: An MCM-HIC device flexibly adds enhanced features to a VLSI “core” IC that are not directly supported by the core IC, such as unsupported communication protocols and/or support of cold spare operation. The core IC is mounted on an interconnecting substrate together with at least one “chiplet” that provides the required feature(s). The chiplet can be programmable. The chiplet can straddle a boundary of an interposer region of the substrate that provides higher density interconnections at lower currents. The disclosed method can include selecting a core IC and at least one active, passive, or “mixed” chiplet, configuring a substrate, and installing the core IC and chiplet(s) on the substrate. In embodiments, the core IC and/or chiplet(s) can be modified before assembly to obtain the desired result. Cost can be reduced by pre-designing and, in embodiments, pre-manufacturing the chiplets and modified core ICs in cost-effective quantities.
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公开(公告)号：US20190045675A1
公开(公告)日：2019-02-07
申请号：US15668017
申请日：2017-08-03
Inventor： Bin Li , Lloyd Brown , Patrick Fleming , Jason F. Ross
Abstract: A system for limiting or diminishing current to unpowered Serializer/Deserializer (SerDes) circuitry is provided. The system comprises receiver input termination circuitry and a cold spare circuitry. The receiver input circuitry comprises a termination resistor and an N-type metal oxide silicon field effect transistor (MOSFET). The cold spare circuitry comprises a first MOSFET and a second MOSFET. When the system is powered on, an input current flows to the receiver input termination circuit to be discharged by the N-type MOSFET which is electrically connected to a ground. When the system is powered off, the input current flows to the cold spare circuitry to discharge the input current. Discharging electrons between the first MOSFET and the second MOSFET depends on the polarity of an accumulated voltage.
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