公开(公告)号：US09997547B2

公开(公告)日：2018-06-12

申请号：US15107070

申请日：2016-02-22

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yueping Zuo ,  Chien Hung Liu ,  Liangjian Li ,  Yinghai Ma

IPC: H01L21/683 ,  H01L27/12

CPC classification number: H01L27/1266

Abstract: The present application discloses a method of fabricating a display apparatus, comprising providing a carrier substrate comprising a base substrate and an adhesive layer over the base substrate, wherein the base substrate comprises a plurality of fluid passages between the base substrate and the adhesive layer, and a plurality of fluid inlets connected with the plurality of fluid passages; forming a product substrate on a side of the adhesive layer distal to the base substrate; dispensing a detaching agent through the plurality of fluid inlets to the plurality of fluid passages, and contacting the detaching agent with the adhesive layer through the plurality of fluid passages; and detaching the product substrate from the carrier substrate.

公开(公告)号：US20170250207A1

公开(公告)日：2017-08-31

申请号：US15309949

申请日：2016-04-08

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Chien Hung Liu

IPC: H01L27/12 ,  H01L29/786

CPC classification number: H01L27/1281 ,  H01L27/1218 ,  H01L27/1222 ,  H01L27/1288 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78675

Abstract: A thin film transistor and a preparation method thereof, an array substrate and a display apparatus are provided. The preparation method includes an operation of forming a low temperature poly silicon active layer; a substrate has a first region and a second region; and the step includes: forming a buffer layer on the first region and the second region of the substrate, the buffer layer having a thickness at a portion corresponding to the first region greater than that at a portion corresponding to the second region; or, forming the buffer layer on the first region of the substrate; forming an amorphous silicon layer on the buffer layer; performing laser crystallization processing on the amorphous silicon layer so as to convert the amorphous silicon layer into a poly silicon layer; and removing the poly silicon layer on the second region, and forming the low temperature poly silicon active layer on the first region.

公开(公告)号：US20170170214A1

公开(公告)日：2017-06-15

申请号：US15443028

申请日：2017-02-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Chunping Long ,  Jang Soon Im ,  Chien Hung Liu

IPC: H01L27/12 ,  H01L21/266 ,  H01L21/265 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1288 ,  G02F1/134363 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/13625 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/77 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3248 ,  H01L27/3262 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78675

Abstract: An array substrate, a manufacturing method thereof, a display device, a thin-film transistor (TFT) and a manufacturing method thereof are disclosed. The method for manufacturing the TFT comprises: forming a pattern of an active layer and a gate insulating layer provided with a metal film on a base substrate; patterning the metal film by one patterning process, and forming patterns of a gate electrode, a source electrode, a drain electrode, a gate line and a data line; forming a passivation layer on the base substrate; patterning the passivation layer by one patterning process, and forming a source contact hole, a drain contact hole and a bridge structure contact hole; and forming a transparent conductive film on the base substrate, and removing partial transparent conductive film to form a source contact portion, a drain contact portion (214), a pixel electrode and a bridge structure. The manufacturing method can reduce the number of the patterning processes.

公开(公告)号：US09543415B2

公开(公告)日：2017-01-10

申请号：US14362971

申请日：2013-12-12

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zuqiang Wang ,  Chien Hung Liu

IPC: H01L21/00 ,  H01L31/062 ,  H01L29/66 ,  H01L27/12 ,  H01L49/02 ,  H01L45/00

CPC classification number: H01L29/66757 ,  H01L27/124 ,  H01L27/1259 ,  H01L27/1288 ,  H01L28/88 ,  H01L45/1691

Abstract: The embodiments of the present invention provide a thin film transistor driving backplane and a manufacturing method thereof, and a display panel. The manufacturing method may comprise: manufacturing a backplane base disposed with a plurality of active device structures; disposing an electrode layer on the backplane base; and manufacturing the electrode layer into a source electrode, a drain electrode and a pixel electrode integrally disposed with the drain electrode by one patterning process. According to the embodiment of the present invention, the electrode layer is manufactured into a plurality of source electrodes, drain electrodes and pixel electrodes, integrally disposed with the drain electrode, by one time patterning process, so that the source electrode, the drain electrode and the pixel electrode are all at the same electrode layer, and the source electrode, the drain electrode and the pixel electrode whose formation needs two patterning processes in the existing method, is simplified to one time patterning process, so it reduces the thickness of the thin film transistor driving backplane, simplifies the manufacturing step, and saves the manufacturing cost.

Abstract translation: 本发明的实施例提供薄膜晶体管驱动背板及其制造方法和显示面板。 制造方法可以包括：制造设置有多个有源器件结构的背板基底; 在背板底座上设置电极层; 并且通过一个图案化工艺将电极层制造成与漏电极整体设置的源电极，漏电极和像素电极。 根据本发明的实施例，通过一次图案化工艺将电极层制造成与漏电极整体配置的多个源电极，漏电极和像素电极，使得源电极，漏电极和 像素电极全部处于相同的电极层，并且在现有方法中形成需要两个图案化处理的源电极，漏电极和像素电极被简化为一次图案化工艺，因此减小了薄的厚度 薄膜晶体管驱动背板，简化了制造步骤，节省了制造成本。