公开(公告)号：US20090207824A1

公开(公告)日：2009-08-20

申请号：US12390359

申请日：2009-02-20

申请人： Thomas H. Lee ,  Michael Palladino ,  Bendik Kleveland ,  Vinay Malekal

发明人： Thomas H. Lee ,  Michael Palladino ,  Bendik Kleveland ,  Vinay Malekal

IPC分类号： H04W84/02

CPC分类号： H04W88/08 ,  H04M2250/06

摘要： A wireless (such as Wi-Fi or similar) access point is included in or attached to a device, such as a cellular phone, WiMAX device, other mobile device, etc. One or more wireless units wirelessly access a communication network (and in some cases the Internet) through the wireless access point device. Additionally, such a wireless access point device can receive a transmission from a wireless tag that has been attached to an object to be monitored and can forward information from the wireless tag to a target device along with location information.

摘要翻译： 无线（例如Wi-Fi或类似的）接入点被包括在诸如蜂窝电话，WiMAX设备，其他移动设备等的设备中或附着到其上。一个或多个无线单元无线地访问通信网络 有些情况下是Internet）通过无线接入点设备。 此外，这样的无线接入点设备可以从已经附接到要监视的对象的无线标签接收传输，并且可以将信息与无线标签一起转发到目标设备以及位置信息。

公开(公告)号：US20090195946A1

公开(公告)日：2009-08-06

申请号：US12026527

申请日：2008-02-05

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： H02H9/04

CPC分类号： H01L27/0251 ,  H01L23/645 ,  H01L23/66 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment of the present invention, an electrostatic discharge protection circuit provides efficient electrostatic discharge protection to an RFIC. The circuit includes several parts such as an inductor coupled from a first rail to an internal node. A power amplifier transistor having a transconductance control node is coupled to internal circuitry, a first terminal coupled to a second rail, and a second terminal coupled to an internal node. The circuit also comprises a pad coupled to an internal node, and this pad is capable of being coupled to off chip systems such as an antenna. The power amplifier transistor serves as the active device for an RF power amplifier. The inductor serves as one of either a bias inductor or a tank inductor for the RF power amplifier. Additionally the inductor acts as a low impedance path to the first rail to protect the power amplifier transistor during an ESD pulse.

摘要翻译： 在本发明的一个实施例中，静电放电保护电路为RFIC提供有效的静电放电保护。 该电路包括几个部件，例如从第一导轨耦合到内部节点的电感器。 具有跨导控制节点的功率放大器晶体管耦合到内部电路，耦合到第二导轨的第一端子和耦合到内部节点的第二端子。 电路还包括耦合到内部节点的焊盘，并且该焊盘能够耦​​合到诸如天线的芯片外系统。 功率放大器晶体管用作RF功率放大器的有源器件。 该电感器用作RF功率放大器的偏置电感器或波导电感器之一。 此外，电感器作为到第一轨道的低阻抗路径，以在ESD脉冲期间保护功率放大器晶体管。

公开(公告)号：US20090052099A1

公开(公告)日：2009-02-26

申请号：US11842043

申请日：2007-08-20

申请人： Yuen Hui Chee ,  Thomas H. Lee ,  Bendik Kleveland

发明人： Yuen Hui Chee ,  Thomas H. Lee ,  Bendik Kleveland

IPC分类号： H02H9/04

CPC分类号： H02H9/046 ,  H04B1/48

摘要： A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.

摘要翻译： 一种用于通信收发器的混合电路（42）。 混合电路（42）将ESD保护电路（12）的功能与TX / RX开关（10）的功能相结合。 混合电路（42）的输入节点在ESD事件（60）的源和被保护的设备（44）之间连接。 混合电路（42）包括由触发晶体管（52）触发的ESD保护元件（50）。 触发晶体管（52）的栅极连接到驱动器（54），用于在传输期间使触发晶体管（52）导通，并在接收期间使触发晶体管（52）关断。

公开(公告)号：US20080278252A1

公开(公告)日：2008-11-13

申请号：US12171281

申请日：2008-07-10

申请人： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

发明人： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

IPC分类号： H03L1/00

CPC分类号： H03L7/099

摘要： A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

摘要翻译： 一种用于校准VCO（10,40）的偏置电流以最小化相位噪声的校准电路（20,50）和方法（60）。 校准电路（20,50）在偏置电流超过预定范围的同时监视VCO（10,40）的共模节点处的平均电压。 校准电路（20,50）识别与最小平均共模电压相关联的偏置电流，并利用该偏置电流来校准VCO（10,40）的偏置晶体管。

公开(公告)号：US07415369B1

公开(公告)日：2008-08-19

申请号：US11801185

申请日：2007-05-08

申请人： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

发明人： Stanley Wang ,  Bendik Kleveland ,  Thomas H. Lee

IPC分类号： G06F19/00

CPC分类号： H03L7/099

摘要： A calibration circuit (20, 50) and method (60) for calibrating the bias current of a VCO (10, 40) to minimize phase noise. The calibration circuit (20, 50) monitors the average voltage at the common-mode node of the VCO (10, 40) while varying the bias current over a predetermined range. The calibration circuit (20, 50) identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO (10, 40).

摘要翻译： 一种用于校准VCO（10,40）的偏置电流以最小化相位噪声的校准电路（20,50）和方法（60）。 校准电路（20,50）在偏置电流超过预定范围的同时监视VCO（10,40）的共模节点处的平均电压。 校准电路（20,50）识别与最小平均共模电压相关联的偏置电流，并利用该偏置电流来校准VCO（10,40）的偏置晶体管。

公开(公告)号：US20070115160A1

公开(公告)日：2007-05-24

申请号：US11600945

申请日：2006-11-16

申请人： Bendik Kleveland ,  Junfeng Xu ,  Thomas Lee ,  Dickson Wong

发明人： Bendik Kleveland ,  Junfeng Xu ,  Thomas Lee ,  Dickson Wong

IPC分类号： H03M1/66

CPC分类号： H04L27/2331

摘要： Apparatus and methods of differentially decoding analog baseband signals are described. In one aspect, a wireless communication apparatus includes a baseband filtering stage and a differential decoder stage. The baseband filtering stage receives a DPSK analog baseband signal differentially encoded with phase shift differences in successive symbol periods. The baseband filtering stage selectively passes frequencies in the DPSK analog baseband signal within a passband frequency range to produce a filtered analog signal. The differential decoder includes a delay circuit and a combiner circuit. The delay circuit produces from the filtered analog signal a reference signal that preserves values of a feature of the filtered analog signal for one symbol period. The combiner circuit combines values of a feature of the filtered analog signal during a current symbol period with values of the reference signal to produce a resultant signal representing a differential decoding of the DPSK analog baseband signal.

摘要翻译： 描述差分解码模拟基带信号的装置和方法。 一方面，无线通信装置包括基带滤波级和差分解码级。 基带滤波级接收在连续符号周期中以相移差差编码的DPSK模拟基带信号。 基带滤波级选择性地通过通带频带范围内的DPSK模拟基带信号中的频率，以产生经滤波的模拟信号。 差分解码器包括延迟电路和组合器电路。 延迟电路从经滤波的模拟信号产生参考信号，该参考信号在一个符号周期内保持滤波后的模拟信号的特征值。 组合器电路将当前符号周期期间滤波的模拟信号的特征值与参考信号的值组合，以产生表示DPSK模拟基带信号的差分解码的结果信号。

公开(公告)号：US06894936B2

公开(公告)日：2005-05-17

申请号：US10623266

申请日：2003-07-18

申请人： Roy E. Scheuerlein ,  Bendik Kleveland

发明人： Roy E. Scheuerlein ,  Bendik Kleveland

IPC分类号： G11C7/04 ,  G11C7/10 ,  G11C7/20 ,  G11C8/12 ,  G11C7/00

CPC分类号： G11C7/04 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/20 ,  G11C8/12 ,  G11C2207/107

摘要： A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.

摘要翻译： 一种用于可选子阵列激活的存储器件和方法。 在一个优选实施例中，提供存储器阵列，其包括多组子阵列和电路，其可操作以同时将数据写入到从所选择的子阵列组中读取数据和/或从所选择的子组组中读取数据。 通过选择数据被写入和/或读取数据的子阵列组的数量，写和/或读数据速率是变化的。 这种变化可以用于防止存储器阵列的热损耗。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。

公开(公告)号：US5898321A

公开(公告)日：1999-04-27

申请号：US824066

申请日：1997-03-24

申请人： Alper Ilkbahar ,  Bendik Kleveland

发明人： Alper Ilkbahar ,  Bendik Kleveland

IPC分类号： H03K17/16 ,  H03K19/0185

CPC分类号： H03K17/164

摘要： A method and an apparatus for adjusting the slew rate and impedance of a buffer in an integrated circuitry. In one embodiment, an integrated circuit buffer includes a pre-driver circuit, which includes a slew rate compensation circuit, coupled to a driver circuit, which includes an impedance compensation circuit. The slew rate compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground to provide a variable resistance to virtual rails for inverter circuits that are included in the pre-driver circuit. The slew rate compensation circuit is digitally controlled with slew rate control signals. The impedance compensation circuit includes parallel connected p-channel transistors to power and parallel connected n-channel transistors to ground from an output node of the buffer. The parallel connected transistors of the impedance compensation circuit are digitally controlled with impedance control signals. The resistance to power and ground from the respective rails of the pre-driver circuit are controlled with the slew rate control signals to adjust the slew rate of data signals being driven by the buffer. The rails are shared among the inverters of the driver circuit to reduce the number of devices used by the buffer, thereby reducing the amount of circuit area and power used by the buffer.

摘要翻译： 一种用于调整集成电路中的缓冲器的转换速率和阻抗的方法和装置。 在一个实施例中，集成电路缓冲器包括预驱动器电路，其包括耦合到驱动器电路的压摆率补偿电路，该驱动器电路包括阻抗补偿电路。 转换速率补偿电路包括并联的p沟道晶体管，以将并联的n沟道晶体管接地，为包括在预驱动器电路中的反相器电路提供可变电阻。 转换速率补偿电路用压摆率控制信号进行数字控制。 阻抗补偿电路包括并联的p沟道晶体管，以将缓冲器的输出节点的N沟道晶体管并联连接到地。 阻抗补偿电路的并联晶体管通过阻抗控制信号进行数字控制。 通过转换速率控制信号控制来自预驱动器电路的相应导轨的电源和接地电阻，以调整由缓冲器驱动的数据信号的转换速率。 轨道在驱动器电路的反相器之间共享，以减少缓冲器使用的设备数量，从而减少缓冲器所使用的电路面积和功率。

公开(公告)号：US07978448B2

公开(公告)日：2011-07-12

申请号：US11842043

申请日：2007-08-20

申请人： Yuen Hui Chee ,  Thomas H. Lee ,  Bendik Kleveland

发明人： Yuen Hui Chee ,  Thomas H. Lee ,  Bendik Kleveland

IPC分类号： H02H9/00

CPC分类号： H02H9/046 ,  H04B1/48

摘要： A hybrid circuit (42) for use with communications transceivers. The hybrid circuit (42) combines the function of an ESD protection circuit (12) with the function of a TX/RX switch (10). The input node of the hybrid circuit (42) is connecting between the source of an ESD event (60) and a device to be protected (44). The hybrid circuit (42) includes an ESD protection element (50), which is triggered by a triggering transistor (52). The gate of the triggering transistor (52) is connected to a driver (54) for turning the triggering transistor (52) on during transmission and for turning the triggering transistor (52) off during reception.

摘要翻译： 一种用于通信收发器的混合电路（42）。 混合电路（42）将ESD保护电路（12）的功能与TX / RX开关（10）的功能相结合。 混合电路（42）的输入节点在ESD事件（60）的源和被保护的设备（44）之间连接。 混合电路（42）包括由触发晶体管（52）触发的ESD保护元件（50）。 触发晶体管（52）的栅极连接到驱动器（54），用于在传输期间使触发晶体管（52）导通，并在接收期间使触发晶体管（52）关断。

公开(公告)号：US20090278517A1

公开(公告)日：2009-11-12

申请号：US12118773

申请日：2008-05-12

申请人： Bendik Kleveland

发明人： Bendik Kleveland

IPC分类号： G05F1/563

CPC分类号： G05F1/563 ,  H02M3/1584 ,  H02M2001/0032 ,  H02M2001/0045 ,  Y02B70/16

摘要： A voltage regulator device and accompanying methods are provided for providing efficient voltage regulation to an electronic device. Efficient regulator 400 receives an input voltage on VIN from a battery or some other power supply at node VIN and supplies a stable regulated voltage to load device 404 at node VOUT. Load device 404 pulls different amounts of current and requires different degrees of tolerance on the voltage at VOUT depending upon its operating conditions. Data collection and control circuit 401 is capable of enabling and disabling regulator 402 and regulator 403. Data collection and control circuit 401 is also capable of measuring certain performance parameters associated with load device 404 and the operating conditions of load device 404. Data collection and control circuit 401 enables regulator 402 if said operating conditions are such that when data collection and control circuit 401 enables regulator 403 the performance parameters associated with load 404 are below a predefined standard.

摘要翻译： 提供了一种电压调节器装置和附带的方法，用于向电子设备提供有效的电压调节。 高效调节器400从节点VIN处的电池或其他电源接收VIN上的输入电压，并在节点VOUT向负载装置404提供稳定的调节电压。 负载装置404拉动不同量的电流，并且根据其工作条件对VOUT上的电压需要不同程度的容差。 数据收集和控制电路401能够启用和禁用调节器402和调节器403.数据收集和控制电路401还能够测量与负载设备404相关联的某些性能参数和负载设备404的操作条件。数据收集和控制 如果所述操作条件使得当数据收集和控制电路401启用调节器403时，与加载404相关联的性能参数低于预定标准，则电路401使得调节器402能够启用调节器402。