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1.发明授权公开(公告)号：US06816410B2
公开(公告)日：2004-11-09
申请号：US10809146
申请日：2004-03-25
IPC分类号： G11C1604
CPC分类号： B82Y10/00 , G11C5/025 , G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0014 , G11C13/0028 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2207/063 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021
摘要： A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
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公开(公告)号：US06515904B2
公开(公告)日：2003-02-04
申请号：US09895960
申请日：2001-06-29
申请人： Christopher S. Moore , Bendik Kleveland , Roger W. March , James M. Cleeves , Roy E. Scheuerlein
发明人： Christopher S. Moore , Bendik Kleveland , Roger W. March , James M. Cleeves , Roy E. Scheuerlein
IPC分类号： G11C1600
摘要： The preferred embodiments described herein provide a method and system for increasing programming bandwidth in a non-volatile memory device. In one preferred embodiment, a memory device is provided with a plurality of bits to be stored in a respective plurality of memory cells along a wordline. Some of the bits represent a programmed state, and others represent an un-programmed state. The duration of the programming pulse applied to the wordline is determined by the number of bits that represent the programmed state. In another preferred embodiment, the plurality of bits to be stored in the memory device comprises a first set of bits representing a modification to the stored data and a second set of bits representing an un-programmed state. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
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公开(公告)号：US06894936B2
公开(公告)日：2005-05-17
申请号：US10623266
申请日：2003-07-18
CPC分类号： G11C7/04 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/20 , G11C8/12 , G11C2207/107
摘要： A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译： 一种用于可选子阵列激活的存储器件和方法。 在一个优选实施例中，提供存储器阵列，其包括多组子阵列和电路，其可操作以同时将数据写入到从所选择的子阵列组中读取数据和/或从所选择的子组组中读取数据。 通过选择数据被写入和/或读取数据的子阵列组的数量，写和/或读数据速率是变化的。 这种变化可以用于防止存储器阵列的热损耗。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。
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公开(公告)号：US07383476B2
公开(公告)日：2008-06-03
申请号：US10774758
申请日：2004-02-09
申请人： Matthew P. Crowley , Luca G. Fasoli , Alper Ilkbahar , Mark G. Johnson , Bendik Kleveland , Thomas H. Lee , Roy E. Scheuerlein
发明人： Matthew P. Crowley , Luca G. Fasoli , Alper Ilkbahar , Mark G. Johnson , Bendik Kleveland , Thomas H. Lee , Roy E. Scheuerlein
CPC分类号： G06F11/1008 , G11C7/22 , G11C17/00
摘要： In one embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array and at least two of the following system blocks: an Error Checking & Correction Circuit (ECC); a Checkerboard Memory Array containing sub arrays; a Write Controller; a Charge Pump; a Vread Generator; an Oscillator; a Band Gap Reference Generator; and a Page Register/Fault Memory. In another embodiment, a chip-level architecture is provided comprising a monolithic three-dimensional write-once memory array, ECC, and smart write. The monolithic three-dimensional write-once memory array comprises a first conductor, a first memory cell above the first conductor, a second conductor above the first memory cell, and a second memory cell above the second conductor, wherein the second conductor is the only conductor between the first and second memory cells.
摘要翻译： 在一个实施例中，提供了包括单片三维一次写入存储器阵列和以下系统块中的至少两个的芯片级结构：错误检查和校正电路（ECC）; 包含子数组的棋盘存储器阵列; 写控制器 电荷泵; Vread发生器; 振荡器 带隙参考发生器; 和页面寄存器/故障存储器。 在另一个实施例中，提供了包括单片三维一次写入存储器阵列ECC和智能写入的芯片级架构。 单片三维一次写入存储器阵列包括第一导体，第一导体上方的第一存储单元，第一存储单元上方的第二导体和第二导体上方的第二存储单元，其中第二导体是唯一的 第一和第二存储单元之间的导体。
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5.发明授权Method for programming a three-dimensional memory array incorporating serial chain diode stack 有权用于编程结合串联链二极管叠层的三维存储阵列的方法公开(公告)号：US06754102B2
公开(公告)日：2004-06-22
申请号：US10253074
申请日：2002-09-24
IPC分类号： G11C1604
CPC分类号： B82Y10/00 , G11C5/025 , G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0014 , G11C13/0028 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2207/063 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021
摘要： A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
摘要翻译： 三维存储器阵列包括在数个级中的每一层上的多个轨道堆叠，形成用于阵列的X线和Y线的交替电平。 存储单元形成在每条X线和Y线的交点处。 每个存储器平面的存储单元都相对于衬底在相同的方向上取向，形成串联链二极管叠层。 在某些实施例中，用于阵列的行和列电路被布置为根据所选择的存储器平面中的存储器单元的方向性来交换功能。 X线和Y线的高电压驱动器都能够根据所选存储单元的方向在任一方向上传递写入电流。 优选的偏置布置反向仅偏离所选择的存储器平面内的未选择的存储器单元，总共大约N 2个存储器单元，而不是像现有的阵列那样大约3N 2个存储器单元。
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公开(公告)号：US06724665B2
公开(公告)日：2004-04-20
申请号：US09943655
申请日：2001-08-31
IPC分类号： G11C700
CPC分类号： G11C7/04 , G11C7/1051 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/20 , G11C8/12 , G11C2207/107
摘要： A memory device and method for selectable sub-array activation. In one preferred embodiment, a memory array is provided comprising a plurality of groups of sub-arrays and circuitry operative to simultaneously write data into and/or read data from a selected number of groups of sub-arrays. By selecting the number of groups of sub-arrays into which data is written and/or from which data is read, the write and/or read data rate is varied. Such varying can be used to prevent thermal run-away of the memory array. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译： 一种用于可选子阵列激活的存储器件和方法。 在一个优选实施例中，提供存储器阵列，其包括多组子阵列和电路，其可操作以同时将数据写入到从所选择的子阵列组中读取数据和/或从所选择的子组组中读取数据。 通过选择数据被写入和/或读取数据的子阵列组的数量，写和/或读数据速率是变化的。 这种变化可以用于防止存储器阵列的热损耗。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。
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公开(公告)号：US06631085B2
公开(公告)日：2003-10-07
申请号：US09897705
申请日：2001-06-29
IPC分类号： G11C1136
CPC分类号： B82Y10/00 , G11C5/025 , G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C8/10 , G11C13/0004 , G11C13/0014 , G11C13/0028 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2207/063 , G11C2213/71 , G11C2213/72 , H01L27/0688 , H01L27/1021
摘要： A three-dimensional memory array includes a plurality of rail-stacks on each of several levels forming alternating levels of X-lines and Y-lines for the array. Memory cells are formed at the intersection of each X-line and Y-line. The memory cells of each memory plane are all oriented in the same direction relative to the substrate, forming a serial chain diode stack. In certain embodiments, row and column circuits for the array are arranged to interchange function depending upon the directionality of memory cells in the selected memory plane. High-voltage drivers for the X-lines and Y-lines are each capable of passing a write current in either direction depending on the direction of the selected memory cell. A preferred bias arrangement reverse biases only unselected memory cells within the selected memory plane, totaling approximately N2 memory cells, rather than approximately 3N2 memory cells as with prior arrays.
摘要翻译： 三维存储器阵列包括在数个级中的每一层上的多个轨道堆叠，形成用于阵列的X线和Y线的交替电平。 存储单元形成在每条X线和Y线的交点处。 每个存储器平面的存储单元都相对于衬底在相同的方向上取向，形成串联链二极管叠层。 在某些实施例中，用于阵列的行和列电路被布置为根据所选择的存储器平面中的存储器单元的方向性来交换功能。 X线和Y线的高电压驱动器都能够根据所选存储单元的方向在任一方向上传递写入电流。 优选的偏置布置反向仅偏离所选择的存储器平面内的未选择的存储器单元，总共大约N 2个存储器单元，而不是像现有的阵列那样大约3N 2个存储器单元。
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公开(公告)号：US06574145B2
公开(公告)日：2003-06-03
申请号：US09896815
申请日：2001-06-29
IPC分类号： G11C1604
CPC分类号： G11C7/062 , G11C7/067 , G11C7/18 , G11C8/08 , G11C17/18 , G11C2013/0066 , G11C2207/063
摘要： The preferred embodiments described herein provide a memory device and method for sensing while programming a non-volatile memory cell. In one preferred embodiment, a memory device is provided with a memory cell and a detection circuit. While the memory cell is being programmed, the detection circuit determines whether the memory cell is in a programmed state. If the memory cell is in a programmed state, the programming of the memory cell is terminated. As compared with prior programming approaches, this preferred embodiment reduces programming time and power while increasing programming bandwidth (the number of memory cells that can be programmed per unit time). In another preferred embodiment, a plurality of memory cells along a wordline are programmed simultaneously. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
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公开(公告)号：US07219271B2
公开(公告)日：2007-05-15
申请号：US10024646
申请日：2001-12-14
CPC分类号： G11C29/72 , G11C29/4401 , G11C29/80
摘要： The preferred embodiments described herein provide a memory device and method for redundancy/self-repair. In one preferred embodiment, a memory device is provided comprising a primary block of memory cells and a redundant block of memory cells. In response to an error in writing to the primary block, a flag is stored in a set of memory cells allocated to the primary block, and the redundant block is written into. In another preferred embodiment, an error in writing to a primary block is detected while an attempt is made to write to that block. In response to the error, the redundant block is written into. In yet another preferred embodiment, a memory device is provided comprising a three-dimensional memory array and redundancy circuitry. In still another preferred embodiment, a method for testing a memory array is provided. Other preferred embodiments are provided, and each of the preferred embodiments described herein can be used alone or in combination with one another.
摘要翻译： 本文所述的优选实施例提供了用于冗余/自修复的存储器件和方法。 在一个优选实施例中，提供存储器件，其包括存储器单元的主块和存储器单元的冗余块。 响应于对主块的写入错误，标志被存储在分配给主块的一组存储器单元中，并且冗余块被写入。 在另一优选实施例中，在尝试写入该块时检测到写入主块的错误。 响应错误，冗余块被写入。 在另一优选实施例中，提供了包括三维存储器阵列和冗余电路的存储器件。 在又一优选实施例中，提供了一种用于测试存储器阵列的方法。 提供了其它优选实施方案，并且本文所述的各优选实施方案可以单独使用或彼此组合使用。
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10.发明授权Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions 有权用于选择一组存储单元层相关或依赖于温度的操作条件的集成电路和方法公开(公告)号：US06954394B2
公开(公告)日：2005-10-11
申请号：US10307270
申请日：2002-11-27
CPC分类号： G11C29/028 , G11C7/04 , G11C7/1045 , G11C7/18 , G11C7/22 , G11C29/50 , G11C29/50012 , G11C2029/5002 , G11C2207/2281 , G11C2207/229
摘要： The preferred embodiments described herein relate to an integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions. In one preferred embodiment, a memory array is provided comprising a plurality of memory cells arranged in L layers stacked vertically above one another in a single integrated circuit. A memory cell layer in the memory array is selected, and one of N sets of memory-cell-layer-dependent writing conditions and/or one of K sets of memory-cell-layer-dependent reading conditions is selected based on the selected memory cell layer. In another preferred embodiment, a temperature of an integrated circuit is measured, and a set of writing conditions and/or a set of reading conditions is selected based on the measured temperature. Other preferred embodiments are provided, and each of the preferred embodiments can be used alone or in combination with one another.
摘要翻译： 本文所述的优选实施例涉及用于选择一组存储单元层相关或依赖于温度的操作条件的集成电路和方法。 在一个优选实施例中，提供一种存储器阵列，其包括布置在单个集成电路中彼此垂直堆叠的L层的多个存储单元。 选择存储器阵列中的存储器单元层，并且基于所选择的存储器来选择N组存储器单元层相关写入条件和/或K组存储器单元层相关读取条件中的一个 细胞层。 在另一个优选实施例中，测量集成电路的温度，并且基于测量的温度选择一组写入条件和/或一组读取条件。 提供了其它优选实施方案，并且每个优选实施方案可以单独使用或彼此组合使用。
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