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公开(公告)号：US07397311B2
公开(公告)日：2008-07-08
申请号：US11439658
申请日：2006-05-24
IPC分类号： H03L7/00
摘要： A first receiver frequency reference is passively coupled to a second receiver by tapping a signal directly from the resonant element, such as a crystal, of an oscillator in the first receiver to drive the input of the second receiver. The sinusoidal signal from the resonant element is relatively free of harmonics and minimizes interference that could be caused by harmonics of a square wave signal coupling or an amplified signal. The oscillator of each receiver can be selectively enabled or disabled to allow the receiver to either generate or receive the frequency reference. This technique of coupling can be used to couple a frequency reference signal between integrated circuit receivers.
摘要翻译： 第一接收机频率参考被动地耦合到第二接收机，通过从第一接收机中的振荡器的谐振元件（例如晶体）直接抽出信号来驱动第二接收机的输入。 来自谐振元件的正弦信号相对没有谐波并且最小化可能由方波信号耦合或放大信号的谐波引起的干扰。 可以选择性地使能或禁用每个接收机的振荡器以允许接收机生成或接收频率参考。 这种耦合技术可用于在集成电路接收器之间耦合频率参考信号。
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公开(公告)号：US20060270372A1
公开(公告)日：2006-11-30
申请号：US11439658
申请日：2006-05-24
IPC分类号： H04B7/00
摘要： A first receiver frequency reference is passively coupled to a second receiver by tapping a signal directly from the resonant element, such as a crystal, of an oscillator in the first receiver to drive the input of the second receiver. The sinusoidal signal from the resonant element is relatively free of harmonics and minimizes interference that could be caused by harmonics of a square wave signal coupling or an amplified signal. The oscillator of each receiver can be selectively enabled or disabled to allow the receiver to either generate or receive the frequency reference. This technique of coupling can be used to couple a frequency reference signal between integrated circuit receivers.
摘要翻译： 第一接收机频率参考被动地耦合到第二接收机，通过从第一接收机中的振荡器的谐振元件（例如晶体）直接抽出信号来驱动第二接收机的输入。 来自谐振元件的正弦信号相对没有谐波并且最小化可能由方波信号耦合或放大信号的谐波引起的干扰。 可以选择性地使能或禁用每个接收机的振荡器以允许接收机生成或接收频率参考。 这种耦合技术可用于在集成电路接收器之间耦合频率参考信号。
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公开(公告)号：US07136626B2
公开(公告)日：2006-11-14
申请号：US10071919
申请日：2002-02-08
申请人： Biagio Bisanti , Stefano Cipriani , Eric Duvivier
发明人： Biagio Bisanti , Stefano Cipriani , Eric Duvivier
CPC分类号： H03C3/0983 , H03C3/0966
摘要： A transmitter architecture (200) provides for a stable and low noise modulator where the modulation bandwidth is uncorrelated to the TX loop bandwidth. The output signal (228) of the TX loop is demodulated by a demodulator (208) and the demodulated signal is compared by a comparator (206) with the modulating input signal (202). The output of the comparator is then used to adjust a digital pre-emphasis filter (204) which preconditions the modulating input signal (202) in the digital domain. The preconditioning approach of the present invention provides for low noise because the transmitter designer can chose a narrow band for the TX loop which will also filter out the noise coming from the additional synthesizer (226) used to down convert the input signal.
摘要翻译： 发射机架构（200）提供稳定和低噪声调制器，其中调制带宽与TX环路带宽不相关。 TX环路的输出信号（228）由解调器（208）解调，并且解调信号由比较器（206）与调制输入信号（202）进行比较。 然后比较器的输出用于调整预编码数字域中的调制输入信号（202）的数字预加重滤波器（204）。 本发明的预处理方法提供低噪声，因为发射机设计者可以为TX环路选择窄带，其也将滤除来自用于下变频输入信号的附加合成器（226）的噪声。
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公开(公告)号：US06806781B2
公开(公告)日：2004-10-19
申请号：US09815831
申请日：2001-03-23
IPC分类号： H03L700
CPC分类号： H03L7/113 , H03B5/1243 , H03B5/1265 , H03B5/1293 , H03J5/246 , H03L7/099
摘要： A voltage controlled oscillator (38) includes an LC tank (20) and a capacitor bank (21). LC tank (20) includes an inductor (12) and a varactor (14). The capacitive output of the varactor is controlled by a control voltage &ngr;. To electronically tune the voltage controlled oscillator, a set of capacitors (24) in the capacitor bank (21) are enabled by a digital control signal based on a frequency comparison with a desired frequency. Once the capacitor bank is set, the frequency can be locked at the desired frequency by the phase lock loop.
摘要翻译： 压控振荡器（38）包括LC箱（20）和电容器组（21）。 LC箱（20）包括电感器（12）和变容二极管（14）。 变容二极管的电容输出由控制电压nu控制。 为了电压调节压控振荡器，电容器组（21）中的一组电容器（24）通过基于与期望频率的频率比较的数字控制信号来实现。 一旦电容器组被置位，频率可以通过锁相环锁定在所需的频率。
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公开(公告)号：US06191629B1
公开(公告)日：2001-02-20
申请号：US09405964
申请日：1999-09-27
申请人： Biagio Bisanti , Akbar Ali
发明人： Biagio Bisanti , Akbar Ali
IPC分类号： H03K3289
CPC分类号： H03K3/2885 , H03K3/289
摘要： A D flip-flop circuit operating in master-slave configuration which has low power consumption and is capable of high-speed operation, and a method for lowering power consumption in such a circuit is provided. The circuit embodiment includes two latches, each with a switching and memory section, and two interlaced current sources. In response to the active high clock signal the master latch memory section uses the current from the first current source while the slave latch switching section uses the current from the second current source, and vice versa. The switching section of each latch is biased with a higher current than the memory section, to provide the circuit with low power consumption. The output current provided to the switching section is preferably substantially twice the magnitude of the current provided to the memory section. The ratio of the currents of the current sources for the switching and memory section is preferably in the range of about 30% to 70%, depending on the clock frequency.
摘要翻译： 提供了具有低功耗并且能够高速运行的主从配置工作的D触发器电路，并且提供了一种降低这种电路中的功耗的方法。 电路实施例包括两个锁存器，每个锁存器具有开关和存储器部分以及两个隔行电流源。 响应于活动的高时钟信号，主锁存存储器部分使用来自第一电流源的电流，而从锁存器切换部分使用来自第二电流源的电流，反之亦然。 每个锁存器的开关部分以比存储器部分更高的电流被偏置，为电路提供低功耗。 提供给切换部分的输出电流优选地是提供给存储器部分的电流的大小的两倍。 取决于时钟频率，开关和存储器部分的电流源的电流比优选在约30％至70％的范围内。
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